mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add Thumb1 support for virtual frame indices.
rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
c546c75459
commit
74d7b0af58
@ -1385,13 +1385,6 @@ needsFrameBaseReg(MachineInstr *MI, unsigned operand) const {
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// FIXME: For testing, return true for all loads/stores and false for
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// everything else. We want to create lots of base regs to shake out bugs.
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//
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// FIXME: This is Thumb2/ARM only for now to keep it simpler.
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ARMFunctionInfo *AFI =
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MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
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if (AFI->isThumb1OnlyFunction())
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return false;
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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@ -1401,6 +1394,7 @@ needsFrameBaseReg(MachineInstr *MI, unsigned operand) const {
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case ARM::t2STRi12: case ARM::t2STRi8:
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case ARM::VLDRS: case ARM::VLDRD:
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case ARM::VSTRS: case ARM::VSTRD:
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case ARM::tSTRspi: case ARM::tLDRspi:
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return true;
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default:
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return false;
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@ -1414,14 +1408,14 @@ materializeFrameBaseRegister(MachineBasicBlock::iterator I,
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unsigned BaseReg, int FrameIdx) const {
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ARMFunctionInfo *AFI =
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I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
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unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
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assert(!AFI->isThumb1OnlyFunction() &&
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"This materializeFrameBaseRegister does not support Thumb1!");
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unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
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(AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
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MachineInstrBuilder MIB =
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BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
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.addFrameIndex(FrameIdx).addImm(0);
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AddDefaultCC(AddDefaultPred(MIB));
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if (!AFI->isThumb1OnlyFunction())
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AddDefaultCC(AddDefaultPred(MIB));
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}
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void
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@ -1469,13 +1463,14 @@ bool ARMBaseRegisterInfo::isBaseRegInRange(const MachineInstr *MI,
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unsigned NumBits = 0;
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unsigned Scale = 1;
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unsigned ImmIdx = 0;
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int InstrOffs;
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int InstrOffs = 0;;
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switch(AddrMode) {
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case ARMII::AddrModeT2_i8:
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case ARMII::AddrModeT2_i12:
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// i8 supports only negative, and i12 supports only positive, so
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// based on Offset sign, consider the appropriate instruction
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Offset += MI->getOperand(i+1).getImm();
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InstrOffs = MI->getOperand(i+1).getImm();
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Scale = 1;
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if (Offset < 0) {
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NumBits = 8;
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Offset = -Offset;
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@ -1509,6 +1504,13 @@ bool ARMBaseRegisterInfo::isBaseRegInRange(const MachineInstr *MI,
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NumBits = 8;
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break;
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}
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case ARMII::AddrModeT1_s: {
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ImmIdx = i+1;
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InstrOffs = MI->getOperand(ImmIdx).getImm();
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NumBits = 5;
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Scale = 4;
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break;
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}
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default:
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llvm_unreachable("Unsupported addressing mode!");
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break;
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@ -363,14 +363,173 @@ static void removeOperands(MachineInstr &MI, unsigned i) {
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MI.RemoveOperand(Op);
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}
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int Thumb1RegisterInfo::
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rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int Offset,
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unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
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{
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// if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
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// version then can pull out Thumb1 specific parts here
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return 0;
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bool Thumb1RegisterInfo::
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rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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if (Opcode == ARM::tADDrSPi) {
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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// Can't use tADDrSPi if it's based off the frame pointer.
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unsigned NumBits = 0;
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unsigned Scale = 1;
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if (FrameReg != ARM::SP) {
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Opcode = ARM::tADDi3;
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MI.setDesc(TII.get(Opcode));
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NumBits = 3;
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} else {
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NumBits = 8;
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Scale = 4;
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assert((Offset & 3) == 0 &&
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"Thumb add/sub sp, #imm immediate must be multiple of 4!");
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}
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unsigned PredReg;
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if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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// Turn it into a move.
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MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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// Remove offset and remaining explicit predicate operands.
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do MI.RemoveOperand(FrameRegIdx+1);
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while (MI.getNumOperands() > FrameRegIdx+1 &&
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(!MI.getOperand(FrameRegIdx+1).isReg() ||
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!MI.getOperand(FrameRegIdx+1).isImm()));
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return true;
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}
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// Common case: small offset, fits into instruction.
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unsigned Mask = (1 << NumBits) - 1;
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if (((Offset / Scale) & ~Mask) == 0) {
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// Replace the FrameIndex with sp / fp
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if (Opcode == ARM::tADDi3) {
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removeOperands(MI, FrameRegIdx);
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MachineInstrBuilder MIB(&MI);
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AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
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.addImm(Offset / Scale));
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} else {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
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}
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return true;
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}
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned Bytes = (Offset > 0) ? Offset : -Offset;
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unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
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// MI would expand into a large number of instructions. Don't try to
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// simplify the immediate.
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if (NumMIs > 2) {
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emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
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*this, dl);
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MBB.erase(II);
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return true;
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}
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if (Offset > 0) {
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// Translate r0 = add sp, imm to
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// r0 = add sp, 255*4
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// r0 = add r0, (imm - 255*4)
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if (Opcode == ARM::tADDi3) {
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removeOperands(MI, FrameRegIdx);
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MachineInstrBuilder MIB(&MI);
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AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
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} else {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
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}
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Offset = (Offset - Mask * Scale);
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MachineBasicBlock::iterator NII = llvm::next(II);
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emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
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*this, dl);
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} else {
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// Translate r0 = add sp, -imm to
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// r0 = -imm (this is then translated into a series of instructons)
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// r0 = add r0, sp
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emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
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MI.setDesc(TII.get(ARM::tADDhirr));
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MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
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MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
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if (Opcode == ARM::tADDi3) {
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MachineInstrBuilder MIB(&MI);
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AddDefaultPred(MIB);
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}
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}
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return true;
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} else {
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unsigned ImmIdx = 0;
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int InstrOffs = 0;
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unsigned NumBits = 0;
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unsigned Scale = 1;
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switch (AddrMode) {
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case ARMII::AddrModeT1_s: {
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ImmIdx = FrameRegIdx+1;
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InstrOffs = MI.getOperand(ImmIdx).getImm();
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NumBits = (FrameReg == ARM::SP) ? 8 : 5;
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Scale = 4;
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break;
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}
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default:
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llvm_unreachable("Unsupported addressing mode!");
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break;
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}
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Offset += InstrOffs * Scale;
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assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
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// Common case: small offset, fits into instruction.
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MachineOperand &ImmOp = MI.getOperand(ImmIdx);
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with sp
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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ImmOp.ChangeToImmediate(ImmedOffset);
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return true;
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}
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bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
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if (AddrMode == ARMII::AddrModeT1_s) {
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// Thumb tLDRspi, tSTRspi. These will change to instructions that use
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// a different base register.
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NumBits = 5;
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Mask = (1 << NumBits) - 1;
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}
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// If this is a thumb spill / restore, we will be using a constpool load to
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// materialize the offset.
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if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
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ImmOp.ChangeToImmediate(0);
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else {
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// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
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ImmedOffset = ImmedOffset & Mask;
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ImmOp.ChangeToImmediate(ImmedOffset);
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Offset &= ~(Mask*Scale);
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}
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}
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return Offset == 0;
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}
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void
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Thumb1RegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
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unsigned BaseReg, int64_t Offset) const {
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MachineInstr &MI = *I;
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int Off = Offset; // ARM doesn't need the general 64-bit offsets
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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bool Done = false;
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Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
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assert (Done && "Unable to resolve frame index!");
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}
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/// saveScavengerRegister - Spill the register so it can be used by the
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@ -458,154 +617,20 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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return 0;
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}
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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if (Opcode == ARM::tADDrSPi) {
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Offset += MI.getOperand(i+1).getImm();
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// Can't use tADDrSPi if it's based off the frame pointer.
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unsigned NumBits = 0;
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unsigned Scale = 1;
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if (FrameReg != ARM::SP) {
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Opcode = ARM::tADDi3;
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MI.setDesc(TII.get(Opcode));
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NumBits = 3;
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} else {
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NumBits = 8;
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Scale = 4;
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assert((Offset & 3) == 0 &&
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"Thumb add/sub sp, #imm immediate must be multiple of 4!");
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}
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unsigned PredReg;
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if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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// Turn it into a move.
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MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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// Remove offset and remaining explicit predicate operands.
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do MI.RemoveOperand(i+1);
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while (MI.getNumOperands() > i+1 &&
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(!MI.getOperand(i+1).isReg() || !MI.getOperand(i+1).isImm()));
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return 0;
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}
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// Common case: small offset, fits into instruction.
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unsigned Mask = (1 << NumBits) - 1;
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if (((Offset / Scale) & ~Mask) == 0) {
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// Replace the FrameIndex with sp / fp
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if (Opcode == ARM::tADDi3) {
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removeOperands(MI, i);
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MachineInstrBuilder MIB(&MI);
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AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
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.addImm(Offset / Scale));
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} else {
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
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}
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return 0;
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}
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned Bytes = (Offset > 0) ? Offset : -Offset;
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unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
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// MI would expand into a large number of instructions. Don't try to
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// simplify the immediate.
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if (NumMIs > 2) {
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emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
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*this, dl);
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MBB.erase(II);
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return 0;
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}
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if (Offset > 0) {
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// Translate r0 = add sp, imm to
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// r0 = add sp, 255*4
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// r0 = add r0, (imm - 255*4)
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if (Opcode == ARM::tADDi3) {
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removeOperands(MI, i);
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MachineInstrBuilder MIB(&MI);
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AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
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} else {
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(Mask);
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}
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Offset = (Offset - Mask * Scale);
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MachineBasicBlock::iterator NII = llvm::next(II);
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emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
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*this, dl);
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} else {
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// Translate r0 = add sp, -imm to
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// r0 = -imm (this is then translated into a series of instructons)
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// r0 = add r0, sp
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emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
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MI.setDesc(TII.get(ARM::tADDhirr));
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MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
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MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
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if (Opcode == ARM::tADDi3) {
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MachineInstrBuilder MIB(&MI);
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AddDefaultPred(MIB);
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}
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}
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// Modify MI as necessary to handle as much of 'Offset' as possible
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assert(AFI->isThumbFunction() &&
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"This eliminateFrameIndex only supports Thumb1!");
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if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
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return 0;
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} else {
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unsigned ImmIdx = 0;
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int InstrOffs = 0;
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unsigned NumBits = 0;
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unsigned Scale = 1;
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switch (AddrMode) {
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case ARMII::AddrModeT1_s: {
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ImmIdx = i+1;
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InstrOffs = MI.getOperand(ImmIdx).getImm();
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NumBits = (FrameReg == ARM::SP) ? 8 : 5;
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Scale = 4;
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break;
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}
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default:
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llvm_unreachable("Unsupported addressing mode!");
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break;
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}
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Offset += InstrOffs * Scale;
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assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
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// Common case: small offset, fits into instruction.
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MachineOperand &ImmOp = MI.getOperand(ImmIdx);
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with sp
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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ImmOp.ChangeToImmediate(ImmedOffset);
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return 0;
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}
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bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
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if (AddrMode == ARMII::AddrModeT1_s) {
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// Thumb tLDRspi, tSTRspi. These will change to instructions that use
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// a different base register.
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NumBits = 5;
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Mask = (1 << NumBits) - 1;
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}
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// If this is a thumb spill / restore, we will be using a constpool load to
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// materialize the offset.
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if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
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ImmOp.ChangeToImmediate(0);
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else {
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// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
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ImmedOffset = ImmedOffset & Mask;
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ImmOp.ChangeToImmediate(ImmedOffset);
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Offset &= ~(Mask*Scale);
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}
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}
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// If we get here, the immediate doesn't fit into the instruction. We folded
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// as much as possible above, handle the rest, providing a register that is
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// SP+LargeImm.
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assert(Offset && "This code isn't needed if offset already handled!");
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = MI.getDesc();
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// Remove predicate first.
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int PIdx = MI.findFirstPredOperandIdx();
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if (PIdx != -1)
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@ -44,13 +44,14 @@ public:
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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// rewrite MI to access 'Offset' bytes from the FP. Return the offset that
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// could not be handled directly in MI.
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int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int Offset,
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unsigned MOVOpc, unsigned ADDriOpc,
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unsigned SUBriOpc) const;
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// rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
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// however much remains to be handled. Return 'true' if no further
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// work is required.
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bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const;
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void resolveFrameIndex(MachineBasicBlock::iterator I,
|
||||
unsigned BaseReg, int64_t Offset) const;
|
||||
bool saveScavengerRegister(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
MachineBasicBlock::iterator &UseMI,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user