6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00
Code Issues Projects Releases Wiki Activity
45221a75fb
llvm-6502/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt

99 lines
1.9 KiB
Plaintext
Raw Normal View History

Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:13:01 +00:00
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
# CHECK: icbi 2, 3
0x7c 0x02 0x1f 0xac
[PowerPC] Add support for dcbtst and icbt (prefetch) Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216339 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-23 23:21:04 +00:00
# CHECK: icbt 0, 5, 31
0x7c 0x05 0xf8 0x2c
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:13:01 +00:00
# CHECK: dcbt 2, 3
0x7c 0x02 0x1a 0x2c
# CHECK: dcbtst 2, 3
0x7c 0x02 0x19 0xec
# CHECK: dcbz 2, 3
0x7c 0x02 0x1f 0xec
# CHECK: dcbst 2, 3
0x7c 0x02 0x18 0x6c
# CHECK: isync
0x4c 0x00 0x01 0x2c
# CHECK: stwcx. 2, 3, 4
0x7c 0x43 0x21 0x2d
# CHECK: stdcx. 2, 3, 4
0x7c 0x43 0x21 0xad
# CHECK: sync 2
0x7c 0x40 0x04 0xac
# CHECK: eieio
0x7c 0x00 0x06 0xac
# CHECK: wait 2
0x7c 0x40 0x00 0x7c
Recognize BookE's mbar instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 23:16:31 +00:00
# CHECK: mbar 1
0x7c 0x20 0x06 0xac
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:13:01 +00:00
# CHECK: dcbf 2, 3
0x7c 0x02 0x18 0xac
Add support for part-word atomics for PPC http://reviews.llvm.org/D8090#inline-67337 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:51:07 +00:00
# CHECK: lbarx 2, 3, 4
0x7c 0x43 0x20 0x68
# CHECK: lharx 2, 3, 4
0x7c 0x43 0x20 0xe8
# CHECK: lwarx 2, 3, 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:13:01 +00:00
0x7c 0x43 0x20 0x28
Add support for part-word atomics for PPC http://reviews.llvm.org/D8090#inline-67337 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:51:07 +00:00
# CHECK: ldarx 2, 3, 4
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:13:01 +00:00
0x7c 0x43 0x20 0xa8
Add support for part-word atomics for PPC http://reviews.llvm.org/D8090#inline-67337 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:51:07 +00:00
# CHECK: lbarx 2, 3, 4, 1
0x7c 0x43 0x20 0x69
# CHECK: lharx 2, 3, 4, 1
0x7c 0x43 0x20 0xe9
# CHECK: lwarx 2, 3, 4, 1
0x7c 0x43 0x20 0x29
# CHECK: ldarx 2, 3, 4, 1
0x7c 0x43 0x20 0xa9
Add a disassembler to the PowerPC backend The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:13:01 +00:00
# CHECK: sync 0
0x7c 0x00 0x04 0xac
# CHECK: sync 0
0x7c 0x00 0x04 0xac
# CHECK: sync 1
0x7c 0x20 0x04 0xac
# CHECK: sync 2
0x7c 0x40 0x04 0xac
# CHECK: wait 0
0x7c 0x00 0x00 0x7c
# CHECK: wait 1
0x7c 0x20 0x00 0x7c
# CHECK: wait 2
0x7c 0x40 0x00 0x7c
# CHECK: mftb 2, 123
0x7c 0x5b 0x1a 0xe6
# CHECK: mftb 2, 268
0x7c 0x4c 0x42 0xe6
# CHECK: mftb 2, 269
0x7c 0x4d 0x42 0xe6
Reference in New Issue Copy Permalink