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[PowerPC] Add support for dcbtst and icbt (prefetch)

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Adds code generation support for dcbtst (data cache prefetch for write) and
icbt (instruction cache prefetch for read - Book E cores only).

We still end up with a 'cannot select' error for the non-supported prefetch
intrinsic forms. This will be fixed in a later commit.

Fixes PR20692.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216339 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-08-23 23:21:04 +00:00
parent 389f13012f
commit 7ca2a7d742
5 changed files with 52 additions and 4 deletions
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15
lib/Target/PowerPC/PPCInstrFormats.td
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@ -478,6 +478,21 @@ class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}
class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> {
bits<4> CT;
bits<5> RA;
bits<5> RB;
let Inst{6} = 0;
let Inst{7-10} = CT;
let Inst{11-15} = RA;
let Inst{16-20} = RB;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> {

9
lib/Target/PowerPC/PPCInstrInfo.td
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@ -1303,8 +1303,15 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
PPC970_DGroup_Single;
def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
"icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
(DCBT xoaddr:$dst)>;
(DCBT xoaddr:$dst)>; // data prefetch for loads
def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
(DCBTST xoaddr:$dst)>; // data prefetch for stores
def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
(ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
// Atomic operations
let usesCustomInserter = 1 in {

25
test/CodeGen/PowerPC/ppc64-prefetch.ll
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@ -1,15 +1,34 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc < %s | FileCheck %s
; RUN: llc -mcpu=a2 < %s | FileCheck %s
define void @test1(i8* %a, ...) nounwind {
entry:
call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
ret void
; CHECK-LABEL: @test1
; CHECK: dcbt
}
declare void @llvm.prefetch(i8*, i32, i32, i32)
; CHECK: @test1
; CHECK: dcbt
define void @test2(i8* %a, ...) nounwind {
entry:
call void @llvm.prefetch(i8* %a, i32 1, i32 3, i32 1)
ret void
; CHECK-LABEL: @test2
; CHECK: dcbtst
}
define void @test3(i8* %a, ...) nounwind {
entry:
call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0)
ret void
; CHECK-LABEL: @test3
; CHECK: icbt
}

3
test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
View File

@ -3,6 +3,9 @@
# CHECK: icbi 2, 3
0x7c 0x02 0x1f 0xac
# CHECK: icbt 0, 5, 31
0x7c 0x05 0xf8 0x2c
# CHECK: dcbt 2, 3
0x7c 0x02 0x1a 0x2c

4
test/MC/PowerPC/ppc64-encoding-bookII.s
View File

@ -8,6 +8,10 @@
# CHECK-LE: icbi 2, 3 # encoding: [0xac,0x1f,0x02,0x7c]
icbi 2, 3
# CHECK-BE: icbt 0, 5, 31 # encoding: [0x7c,0x05,0xf8,0x2c]
# CHECK-LE: icbt 0, 5, 31 # encoding: [0x2c,0xf8,0x05,0x7c]
icbt 0, 5, 31
# FIXME: dcbt 2, 3, 10
# CHECK-BE: dcbt 2, 3 # encoding: [0x7c,0x02,0x1a,0x2c]
# CHECK-LE: dcbt 2, 3 # encoding: [0x2c,0x1a,0x02,0x7c]