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llvm-6502/test/CodeGen/CellSPU/div_ops.ll

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; RUN: llc --march=cellspu %s -o - | FileCheck %s
; signed division rounds towards zero, rotma don't.
define i32 @sdivide (i32 %val )
{
; CHECK: rotmai
; CHECK: rotmi
; CHECK: a
; CHECK: rotmai
; CHECK: bi $lr
%rv = sdiv i32 %val, 4
ret i32 %rv
}
define i32 @udivide (i32 %val )
{
; CHECK: rotmi
; CHECK: bi $lr
%rv = udiv i32 %val, 4
ret i32 %rv
}