llvm-6502/test/CodeGen
Jakob Stoklund Olesen e3b548219f Correctly deal with identity copies in RegisterCoalescer.
Now that the coalescer keeps live intervals and machine code in sync at
all times, it needs to deal with identity copies differently.

When merging two virtual registers, all identity copies are removed
right away. This means that other identity copies must come from
somewhere else, and they are going to have a value number.

Deal with such copies by merging the value numbers before erasing the
copy instruction. Otherwise, we leave dangling value numbers in the live
interval.

This fixes PR12927.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23 20:21:06 +00:00
..
ARM [arm-fast-isel] Add support for non-global callee. 2012-05-23 18:38:57 +00:00
CellSPU
CPP
Generic revert my previous patches that introduced an additional parameter to the objectsize intrinsic. 2012-05-22 15:25:31 +00:00
Hexagon Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
MBlaze
Mips Add support for the 'd' mips inline asm output modifier. 2012-05-19 00:51:56 +00:00
MSP430
NVPTX This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. 2012-05-04 20:18:50 +00:00
PowerPC Add a missing PPC 64-bit stwu pattern. 2012-05-20 17:11:24 +00:00
PTX
SPARC Regression test for PR2960. 2012-05-01 11:11:34 +00:00
Thumb Make test less fragile. 2012-04-27 20:48:18 +00:00
Thumb2 FileCheck'ize test, and add a bit to test for r157221. 2012-05-21 23:50:00 +00:00
X86 Correctly deal with identity copies in RegisterCoalescer. 2012-05-23 20:21:06 +00:00
XCore