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llvm-6502/test/CodeGen/Mips/msa/basic_operations_float.ll

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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 10:08:31 +00:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
@v2f64 = global <2 x double> <double 0.0, double 0.0>
define void @const_v4f32() nounwind {
; MIPS32: const_v4f32:
store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
ret void
; MIPS32: .size const_v4f32
}
define void @const_v2f64() nounwind {
; MIPS32: const_v2f64:
store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
ret void
; MIPS32: .size const_v2f64
}
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