2013-11-26 02:03:25 +00:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
|
2013-11-08 23:28:16 +00:00
|
|
|
|
|
|
|
; Stackmap Header: no constants - 6 callsites
|
|
|
|
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
|
|
|
|
; CHECK-NEXT: __LLVM_StackMaps:
|
|
|
|
; Header
|
|
|
|
; CHECK-NEXT: .long 0
|
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|
|
; Num Constants
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Num Callsites
|
2013-11-19 03:29:59 +00:00
|
|
|
; CHECK-NEXT: .long 8
|
2013-11-08 23:28:16 +00:00
|
|
|
|
|
|
|
; test
|
2013-11-11 22:40:25 +00:00
|
|
|
; CHECK-LABEL: .long L{{.*}}-_test
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
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|
|
; 3 locations
|
|
|
|
; CHECK-NEXT: .short 3
|
|
|
|
; Loc 0: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 4
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 1: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 4
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 2: Constant 3
|
|
|
|
; CHECK-NEXT: .byte 4
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
|
|
|
; CHECK-NEXT: .long 3
|
|
|
|
define i64 @test() nounwind ssp uwtable {
|
|
|
|
entry:
|
2013-11-09 01:51:33 +00:00
|
|
|
call anyregcc void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
|
2013-11-08 23:28:16 +00:00
|
|
|
ret i64 0
|
|
|
|
}
|
|
|
|
|
|
|
|
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
|
2013-11-11 22:40:25 +00:00
|
|
|
; CHECK-LABEL: .long L{{.*}}-_property_access1
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
|
|
|
; 2 locations
|
|
|
|
; CHECK-NEXT: .short 2
|
|
|
|
; Loc 0: Register <-- this is the return register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 1: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
|
|
|
|
entry:
|
|
|
|
%f = inttoptr i64 12297829382473034410 to i8*
|
2013-11-09 01:51:33 +00:00
|
|
|
%ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 1, i32 15, i8* %f, i32 1, i8* %obj)
|
2013-11-08 23:28:16 +00:00
|
|
|
ret i64 %ret
|
|
|
|
}
|
|
|
|
|
|
|
|
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
|
2013-11-11 22:40:25 +00:00
|
|
|
; CHECK-LABEL: .long L{{.*}}-_property_access2
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
|
|
|
; 2 locations
|
|
|
|
; CHECK-NEXT: .short 2
|
|
|
|
; Loc 0: Register <-- this is the return register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 1: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
define i64 @property_access2() nounwind ssp uwtable {
|
|
|
|
entry:
|
|
|
|
%obj = alloca i64, align 8
|
|
|
|
%f = inttoptr i64 12297829382473034410 to i8*
|
2013-11-09 01:51:33 +00:00
|
|
|
%ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 2, i32 15, i8* %f, i32 1, i64* %obj)
|
2013-11-08 23:28:16 +00:00
|
|
|
ret i64 %ret
|
|
|
|
}
|
|
|
|
|
|
|
|
; property access 3 - %obj is a frame index
|
2013-11-11 22:40:25 +00:00
|
|
|
; CHECK-LABEL: .long L{{.*}}-_property_access3
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
|
|
|
; 2 locations
|
|
|
|
; CHECK-NEXT: .short 2
|
|
|
|
; Loc 0: Register <-- this is the return register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
2013-11-26 02:03:25 +00:00
|
|
|
; Loc 1: Direct RBP - ofs
|
|
|
|
; CHECK-NEXT: .byte 2
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-26 02:03:25 +00:00
|
|
|
; CHECK-NEXT: .short 6
|
|
|
|
; CHECK-NEXT: .long
|
2013-11-08 23:28:16 +00:00
|
|
|
define i64 @property_access3() nounwind ssp uwtable {
|
|
|
|
entry:
|
|
|
|
%obj = alloca i64, align 8
|
|
|
|
%f = inttoptr i64 12297829382473034410 to i8*
|
2013-11-09 01:51:33 +00:00
|
|
|
%ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 3, i32 15, i8* %f, i32 0, i64* %obj)
|
2013-11-08 23:28:16 +00:00
|
|
|
ret i64 %ret
|
|
|
|
}
|
|
|
|
|
|
|
|
; anyreg_test1
|
2013-11-11 22:40:25 +00:00
|
|
|
; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
2013-11-09 01:51:33 +00:00
|
|
|
; 14 locations
|
|
|
|
; CHECK-NEXT: .short 14
|
2013-11-08 23:28:16 +00:00
|
|
|
; Loc 0: Register <-- this is the return register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 1: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 2: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 3: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 4: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 5: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 6: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 7: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 8: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 9: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 10: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 11: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 12: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 13: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
2013-11-09 01:51:33 +00:00
|
|
|
define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
|
2013-11-08 23:28:16 +00:00
|
|
|
entry:
|
|
|
|
%f = inttoptr i64 12297829382473034410 to i8*
|
2013-11-09 01:51:33 +00:00
|
|
|
%ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
|
2013-11-08 23:28:16 +00:00
|
|
|
ret i64 %ret
|
|
|
|
}
|
|
|
|
|
|
|
|
; anyreg_test2
|
2013-11-11 22:40:25 +00:00
|
|
|
; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short 0
|
2013-11-09 01:51:33 +00:00
|
|
|
; 14 locations
|
|
|
|
; CHECK-NEXT: .short 14
|
2013-11-08 23:28:16 +00:00
|
|
|
; Loc 0: Register <-- this is the return register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 1: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 2: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 3: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 4: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 5: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 6: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 7: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 8: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 9: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 10: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 11: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 12: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
|
|
|
; Loc 13: Register
|
|
|
|
; CHECK-NEXT: .byte 1
|
2013-11-17 01:36:23 +00:00
|
|
|
; CHECK-NEXT: .byte 8
|
2013-11-08 23:28:16 +00:00
|
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
|
|
; CHECK-NEXT: .long 0
|
2013-11-09 01:51:33 +00:00
|
|
|
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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2013-11-08 23:28:16 +00:00
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entry:
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%f = inttoptr i64 12297829382473034410 to i8*
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2013-11-09 01:51:33 +00:00
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%ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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2013-11-08 23:28:16 +00:00
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ret i64 %ret
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}
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2013-11-11 22:40:25 +00:00
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; Test spilling the return value of an anyregcc call.
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;
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; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
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;
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; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 3
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; Loc 0: Register (some register that will be spilled to the stack)
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; CHECK-NEXT: .byte 1
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2013-11-17 01:36:23 +00:00
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; CHECK-NEXT: .byte 8
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2013-11-11 22:40:25 +00:00
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register RDI
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; CHECK-NEXT: .byte 1
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2013-11-17 01:36:23 +00:00
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; CHECK-NEXT: .byte 8
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2013-11-11 22:40:25 +00:00
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; CHECK-NEXT: .short 5
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; CHECK-NEXT: .long 0
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; Loc 1: Register RSI
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; CHECK-NEXT: .byte 1
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2013-11-17 01:36:23 +00:00
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; CHECK-NEXT: .byte 8
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2013-11-11 22:40:25 +00:00
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .long 0
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define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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%result = tail call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
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tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
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ret i64 %result
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}
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2013-11-19 03:29:59 +00:00
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; Test spilling the arguments of an anyregcc call.
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;
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; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
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;
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; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 5
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; Loc 0: Return a register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Arg0 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Arg1 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Arg2 spilled to RBP +
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 8
|
2013-11-26 02:03:25 +00:00
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
|
2013-11-19 03:29:59 +00:00
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|
; Loc 4: Arg3 spilled to RBP +
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 8
|
2013-11-26 02:03:25 +00:00
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
|
2013-11-19 03:29:59 +00:00
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|
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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|
|
|
entry:
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|
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|
tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
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|
%result = tail call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
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ret i64 %result
|
|
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|
}
|
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|
2013-11-08 23:28:16 +00:00
|
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declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)
|