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llvm-6502/test/MC/Disassembler/X86/intel-syntax.txt

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Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible. The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 11:32:10 +00:00
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 --output-asm-variant=1 | FileCheck %s
Add disassembler test for Intel syntax. Tests r139353. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 06:35:44 +00:00
# CHECK: movsb
0xa4
# CHECK: movsw
0x66 0xa5
# CHECK: movsd
0xa5
# CHECK: movsq
0x48 0xa5
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 07:01:50 +00:00
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 06:57:25 +00:00
# CHECK: pop FS
0x0f 0xa1
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 07:01:50 +00:00
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 06:57:25 +00:00
# CHECK: pop GS
0x0f 0xa9
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 07:01:50 +00:00
# CHECK: in AL, DX
0xec
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
# CHECK: nop
0x90
# CHECK: xchg EAX, R8D
0x41 0x90
# CHECK: xchg RAX, R8
0x49 0x90
# CHECK: add AL, 0
0x04 0x00
# CHECK: add AX, 0
0x66 0x05 0x00 0x00
# CHECK: add EAX, 0
0x05 0x00 0x00 0x00 0x00
# CHECK: add RAX, 0
0x48 0x05 0x00 0x00 0x00 0x00
# CHECK: adc AL, 0
0x14 0x00
# CHECK: adc AX, 0
0x66 0x15 0x00 0x00
# CHECK: adc EAX, 0
0x15 0x00 0x00 0x00 0x00
# CHECK: adc RAX, 0
0x48 0x15 0x00 0x00 0x00 0x00
# CHECK: cmp AL, 0
0x3c 0x00
# CHECK: cmp AX, 0
0x66 0x3d 0x00 0x00
# CHECK: cmp EAX, 0
0x3d 0x00 0x00 0x00 0x00
# CHECK: cmp RAX, 0
0x48 0x3d 0x00 0x00 0x00 0x00
# CHECK: test AL, 0
0xa8 0x00
# CHECK: test AX, 0
0x66 0xa9 0x00 0x00
# CHECK: test EAX, 0
0xa9 0x00 0x00 0x00 0x00
# CHECK: test RAX, 0
0x48 0xa9 0x00 0x00 0x00 0x00
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax. Patch by Kay Tiong Khoo! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 07:37:27 +00:00
# CHECK: sysret
0x48 0x0f 0x07
# CHECK: sysret
0x0f 0x07
# CHECK: sysexit
0x48 0x0f 0x35
# CHECK: sysexit
0x0f 0x35
# CHECK: iret
0x66 0xcf
# CHECK: iretd
0xcf
# CHECK: iretq
0x48 0xcf
Add retw and lretw instructions. Also, fix Intel syntax parsing for all ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 01:10:53 +00:00
# CHECK: ret
0x66 0xc3
# CHECK: retf
0x66 0xcb
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18 04:11:12 +00:00
# CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0
0xc4 0xe2 0xfd 0x91 0x14 0x4f
# CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
0xc4 0x02 0x39 0x90 0x14 0x4f
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 21:52:25 +00:00
# CHECK: xsave64 OPAQUE PTR [RAX]
0x48 0x0f 0xae 0x20
# CHECK: xrstor64 OPAQUE PTR [RAX]
0x48 0x0f 0xae 0x28
# CHECK: xsaveopt64 OPAQUE PTR [RAX]
0x48 0x0f 0xae 0x30
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