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Add retw and lretw instructions. Also, fix Intel syntax parsing for all

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ret instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Charles Davis 2012-04-11 01:10:53 +00:00
parent a0908d0a44
commit 0d82fe77f2
5 changed files with 41 additions and 5 deletions
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15
lib/Target/X86/X86InstrControl.td
View File

@ -21,20 +21,25 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
"ret",
[(X86retflag 0)], IIC_RET>;
def RETW : I <0xC3, RawFrm, (outs), (ins variable_ops),
"ret{w}",
[], IIC_RET>, OpSize;
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret\t$amt",
[(X86retflag timm:$amt)], IIC_RET_IMM>;
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"retw\t$amt",
"ret{w}\t$amt",
[], IIC_RET_IMM>, OpSize;
def LRETL : I <0xCB, RawFrm, (outs), (ins),
"lretl", [], IIC_RET>;
"{l}ret{l|f}", [], IIC_RET>;
def LRETW : I <0xCB, RawFrm, (outs), (ins),
"{l}ret{w|f}", [], IIC_RET>, OpSize;
def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
"lretq", [], IIC_RET>;
"{l}ret{q|f}", [], IIC_RET>;
def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"lret\t$amt", [], IIC_RET>;
"{l}ret{l|f}\t$amt", [], IIC_RET>;
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"lretw\t$amt", [], IIC_RET>, OpSize;
"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
}
// Unconditional branches.

6
test/MC/Disassembler/X86/intel-syntax.txt
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@ -99,3 +99,9 @@
# CHECK: iretq
0x48 0xcf
# CHECK: ret
0x66 0xc3
# CHECK: retf
0x66 0xcb

13
test/MC/X86/intel-syntax-encoding.s
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@ -42,3 +42,16 @@ LBB0_3:
// CHECK: encoding: [0x0f,0xc2,0xd1,0x01]
cmpltps XMM2, XMM1
// CHECK: encoding: [0xc3]
ret
// CHECK: encoding: [0xcb]
retf
// CHECK: encoding: [0xc2,0x08,0x00]
ret 8
// CHECK: encoding: [0xca,0x08,0x00]
retf 8

8
test/MC/X86/x86-32.s
View File

@ -990,3 +990,11 @@ xchgl %ecx, %eax
// CHECK: xchgl %ecx, %eax
// CHECK: encoding: [0x91]
xchgl %eax, %ecx
// CHECK: retw
// CHECK: encoding: [0x66,0xc3]
retw
// CHECK: lretw
// CHECK: encoding: [0x66,0xcb]
lretw

4
test/MC/X86/x86-64.s
View File

@ -50,6 +50,9 @@
// CHECK: ret
ret
// CHECK: retw
retw
// FIXME: Check that this matches SUB32ri8
// CHECK: subl $1, %eax
subl $1, %eax
@ -841,6 +844,7 @@ iretq
lretq // CHECK: lretq # encoding: [0x48,0xcb]
lretl // CHECK: lretl # encoding: [0xcb]
lret // CHECK: lretl # encoding: [0xcb]
lretw // CHECK: lretw # encoding: [0x66,0xcb]
// rdar://8403907
sysret