2009-11-17 00:20:26 +00:00
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; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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2009-07-07 20:39:03 +00:00
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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2009-11-17 00:20:26 +00:00
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; CHECK: t1
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2010-11-17 20:13:28 +00:00
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; CHECK: mvn r0, #-2147483648
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2009-11-17 00:20:26 +00:00
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; CHECK: cmp r2, #10
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2012-08-16 23:21:55 +00:00
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; CHECK: it le
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Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
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; CHECK: addle r1, r0
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2012-08-16 23:21:55 +00:00
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; CHECK: mov r0, r1
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2009-07-07 20:39:03 +00:00
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
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2009-11-17 00:20:26 +00:00
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; CHECK: t2
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; CHECK: cmp r2, #10
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2012-08-16 23:21:55 +00:00
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; CHECK: it le
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; CHECK: addle.w r1, r1, #-2147483648
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; CHECK: mov r0, r1
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2009-11-17 00:20:26 +00:00
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2009-07-07 20:39:03 +00:00
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483648
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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2009-11-17 00:20:26 +00:00
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; CHECK: t3
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; CHECK: cmp r2, #10
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2012-08-16 23:21:55 +00:00
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; CHECK: it le
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
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; CHECK: suble r1, #10
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2012-08-16 23:21:55 +00:00
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; CHECK: mov r0, r1
|
2009-07-07 20:39:03 +00:00
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 10
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%tmp3 = sub i32 %b, %tmp2
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ret i32 %tmp3
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}
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