llvm-6502/test/CodeGen/R600/insert_subreg.ll

; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s

; Test that INSERT_SUBREG instructions don't have non-register operands after
; instruction selection.

; Make sure this doesn't crash
; CHECK-LABEL: test:
define void @test(i64 addrspace(1)* %out) {
entry:
  %tmp0 = alloca [16 x i32]
  %tmp1 = ptrtoint [16 x i32]* %tmp0 to i32
  %tmp2 = sext i32 %tmp1 to i64
  store i64 %tmp2, i64 addrspace(1)* %out
  ret void
}
R600/SI: Add a stub GCNTargetMachine This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8 2015-01-06 18:00:21 +00:00			`; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s`
R600/SI: Enable all tests that pass on VI without changes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227214 91177308-0d34-0410-b5e6-96231b3b80d8 2015-01-27 17:27:15 +00:00			`; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s`
R600/SI: Legalize INSERT_SUBREG instructions during PostISelFolding LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219420 91177308-0d34-0410-b5e6-96231b3b80d8 2014-10-09 18:09:15 +00:00
			`; Test that INSERT_SUBREG instructions don't have non-register operands after`
			`; instruction selection.`

			`; Make sure this doesn't crash`
			`; CHECK-LABEL: test:`
			`define void @test(i64 addrspace(1)* %out) {`
			`entry:`
			`%tmp0 = alloca [16 x i32]`
			`%tmp1 = ptrtoint [16 x i32]* %tmp0 to i32`
			`%tmp2 = sext i32 %tmp1 to i64`
			`store i64 %tmp2, i64 addrspace(1)* %out`
			`ret void`
			`}`