2012-10-10 22:25:11 +00:00
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; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
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2012-10-10 21:25:01 +00:00
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; This verifies that we generate correct spill/reload code for vector regs.
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define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
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entry:
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%i.addr = alloca i32, align 4
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%w.addr = alloca <4 x float>, align 16
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store i32 %i, i32* %i.addr, align 4
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store <4 x float> %w, <4 x float>* %w.addr, align 16
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call void @foo(i32* %i.addr)
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ret void
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}
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; CHECK: stvx 2, 0, 0
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; CHECK: lvx 2, 0, 0
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declare void @foo(i32*)
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