Jyotsna Verma 6b8d2026ba Hexagon: Add support to generate predicated absolute addressing mode ... instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-12 16:06:23 +00:00
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AArch64	Implement external weak (ELF) symbols on AArch64	2013-02-06 16:43:33 +00:00
ARM	ARM NEON: Handle v16i8 and v8i16 reverse shuffles	2013-02-12 01:58:32 +00:00
CPP
Generic
Hexagon	Hexagon: Add support to generate predicated absolute addressing mode	2013-02-12 16:06:23 +00:00
MBlaze
Mips	Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the	2013-02-08 21:42:56 +00:00
MSP430
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	DAGCombiner: Constant folding around pre-increment loads/stores	2013-02-08 21:35:47 +00:00
R600	R600: Add support for SET*_DX10 instructions	2013-02-07 14:02:35 +00:00
SI
SPARC
Thumb
Thumb2
X86	PR14562 - Truncation of left shift became undef	2013-02-12 15:21:21 +00:00
XCore