2015-01-06 18:00:21 +00:00
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=CI -check-prefix=FUNC %s
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2014-06-11 18:08:48 +00:00
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
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2015-01-29 16:55:25 +00:00
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; SI: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
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2014-11-05 14:50:53 +00:00
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; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; SI-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
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; SI: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0]
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; SI: s_endpgm
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2014-06-11 18:08:48 +00:00
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define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap) nounwind {
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%gep = getelementptr i32 addrspace(3)* %ptr, i32 4
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IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:07 +00:00
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%pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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2014-06-11 18:08:48 +00:00
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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2014-06-11 18:08:54 +00:00
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset:
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2015-01-07 20:27:25 +00:00
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; SI-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
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; SI-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
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2015-01-29 16:55:25 +00:00
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; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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2014-11-05 14:50:53 +00:00
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; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; SI-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
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; SI-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
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; SI: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
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; SI: buffer_store_dwordx2 [[RESULT]],
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; SI: s_endpgm
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2014-06-11 18:08:54 +00:00
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define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
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%gep = getelementptr i64 addrspace(3)* %ptr, i32 4
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IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:07 +00:00
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%pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
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%result = extractvalue { i64, i1 } %pair, 0
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2014-06-11 18:08:54 +00:00
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store i64 %result, i64 addrspace(1)* %out, align 8
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ret void
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}
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2014-09-05 16:24:58 +00:00
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2014-10-10 22:16:07 +00:00
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; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset
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2014-11-05 14:50:53 +00:00
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; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0]
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; SI: s_endpgm
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2014-09-05 16:24:58 +00:00
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define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
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%sub = sub i32 %a, %b
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%add = add i32 %sub, 4
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%gep = getelementptr i32 addrspace(3)* %ptr, i32 %add
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%pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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2014-09-08 15:07:31 +00:00
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i32_offset:
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2014-11-05 14:50:53 +00:00
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; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
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; SI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa
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; SI-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
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; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; SI-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
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; SI: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0]
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; SI: s_endpgm
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2014-09-08 15:07:31 +00:00
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define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %swap) nounwind {
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%gep = getelementptr i32 addrspace(3)* %ptr, i32 4
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%pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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ret void
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}
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset:
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2014-11-05 14:50:53 +00:00
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; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
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; SI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
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2015-01-07 20:27:25 +00:00
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; SI-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
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; SI-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
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2014-11-05 14:50:53 +00:00
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; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; SI-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
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; SI-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
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; SI: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
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; SI: s_endpgm
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2014-09-08 15:07:31 +00:00
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define void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
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%gep = getelementptr i64 addrspace(3)* %ptr, i32 4
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%pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
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%result = extractvalue { i64, i1 } %pair, 0
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ret void
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}
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