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llvm-6502/lib/Target/X86/Makefile

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Makefile
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Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
LEVEL = ../../..
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
# Make sure that tblgen is run, first thing.
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
X86GenInstrInfo.inc X86GenInstrSelector.inc
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
X86GenRegisterNames.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
$(TBLGEN) $< -gen-register-enums -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
$(TBLGEN) $< -gen-register-desc-header -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
$(TBLGEN) $< -gen-register-desc -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
X86GenInstrNames.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
$(TBLGEN) $< -gen-instr-enums -o $@
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
X86GenInstrInfo.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
$(TBLGEN) $< -gen-instr-desc -o $@
X86GenInstrSelector.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
Whoops, accidental checkin. :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7743 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 19:35:46 +00:00
$(TBLGEN) $< -gen-instr-selector -o $@
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
clean::
$(VERB) rm -f *.inc
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