2012-12-11 21:25:42 +00:00
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//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU target machine contains all of the hardware specific
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/// information needed to emit code for R600 and SI GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPU.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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2013-03-05 18:41:32 +00:00
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#include "R600MachineScheduler.h"
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2012-12-11 21:25:42 +00:00
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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2014-01-13 09:26:24 +00:00
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#include "llvm/IR/Verifier.h"
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2012-12-11 21:25:42 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_os_ostream.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Scalar.h"
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#include <llvm/CodeGen/Passes.h>
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using namespace llvm;
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extern "C" void LLVMInitializeR600Target() {
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// Register the target
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RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
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}
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2013-03-05 18:41:32 +00:00
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static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
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2014-04-21 20:32:32 +00:00
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return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
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2013-03-05 18:41:32 +00:00
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}
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static MachineSchedRegistry
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SchedCustomRegistry("r600", "Run R600's custom scheduler",
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createR600MachineScheduler);
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2012-12-11 21:25:42 +00:00
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AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
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2014-07-25 22:22:39 +00:00
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StringRef CPU, StringRef FS,
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TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OptLevel)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
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2014-08-04 17:37:43 +00:00
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Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
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2013-12-07 01:49:19 +00:00
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setRequiresStructuredCFG(true);
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2013-05-13 01:16:13 +00:00
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initAsmInfo();
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2012-12-11 21:25:42 +00:00
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}
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AMDGPUTargetMachine::~AMDGPUTargetMachine() {
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}
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namespace {
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class AMDGPUPassConfig : public TargetPassConfig {
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public:
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AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
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2013-09-20 05:14:41 +00:00
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: TargetPassConfig(TM, PM) {}
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2012-12-11 21:25:42 +00:00
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AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
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return getTM<AMDGPUTargetMachine>();
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}
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2013-09-20 05:14:41 +00:00
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2014-04-29 07:57:24 +00:00
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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2013-09-20 05:14:41 +00:00
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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return createR600MachineScheduler(C);
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2014-04-25 05:30:21 +00:00
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return nullptr;
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2013-09-20 05:14:41 +00:00
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}
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2014-09-03 11:41:21 +00:00
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void addCodeGenPrepare() override;
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2014-04-29 07:57:24 +00:00
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addPreRegAlloc() override;
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bool addPostRegAlloc() override;
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bool addPreSched2() override;
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bool addPreEmitPass() override;
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2012-12-11 21:25:42 +00:00
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};
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} // End of anonymous namespace
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TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AMDGPUPassConfig(this, PM);
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}
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2013-07-27 00:01:07 +00:00
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//===----------------------------------------------------------------------===//
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// AMDGPU Analysis Pass Setup
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//===----------------------------------------------------------------------===//
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void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
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// allows the AMDGPU pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createAMDGPUTargetTransformInfoPass(this));
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}
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2014-06-17 16:53:14 +00:00
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void AMDGPUPassConfig::addCodeGenPrepare() {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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2014-07-13 02:08:26 +00:00
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if (ST.isPromoteAllocaEnabled()) {
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addPass(createAMDGPUPromoteAlloca(ST));
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addPass(createSROAPass());
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}
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2014-06-17 16:53:14 +00:00
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TargetPassConfig::addCodeGenPrepare();
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}
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2012-12-11 21:25:42 +00:00
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bool
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AMDGPUPassConfig::addPreISel() {
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2012-12-19 22:10:31 +00:00
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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2013-08-06 02:43:45 +00:00
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addPass(createFlattenCFGPass());
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2013-11-18 19:43:44 +00:00
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if (ST.IsIRStructurizerEnabled())
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2013-10-10 17:11:12 +00:00
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addPass(createStructurizeCFGPass());
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2014-02-24 21:01:23 +00:00
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if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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2013-10-13 17:56:21 +00:00
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addPass(createSinkingPass());
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2013-08-14 23:24:45 +00:00
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addPass(createSITypeRewriter());
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2012-12-19 22:10:31 +00:00
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addPass(createSIAnnotateControlFlowPass());
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2013-05-17 16:50:20 +00:00
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} else {
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addPass(createR600TextureIntrinsicsReplacer());
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2012-12-19 22:10:31 +00:00
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}
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2012-12-11 21:25:42 +00:00
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return false;
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}
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bool AMDGPUPassConfig::addInstSelector() {
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addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
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2014-04-30 15:31:33 +00:00
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addPass(createSILowerI1CopiesPass());
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2012-12-11 21:25:42 +00:00
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return false;
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}
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bool AMDGPUPassConfig::addPreRegAlloc() {
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2013-06-05 21:38:04 +00:00
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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2013-06-07 20:37:48 +00:00
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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2013-06-05 21:38:04 +00:00
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addPass(createR600VectorRegMerger(*TM));
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2013-08-06 23:08:28 +00:00
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} else {
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addPass(createSIFixSGPRCopiesPass(*TM));
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2014-03-21 15:51:57 +00:00
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// SIFixSGPRCopies can generate a lot of duplicate instructions,
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// so we need to run MachineCSE afterwards.
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addPass(&MachineCSEID);
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2014-07-21 16:55:33 +00:00
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addPass(createSIShrinkInstructionsPass());
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2014-07-02 20:53:48 +00:00
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initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
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insertPass(&RegisterCoalescerID, &SIFixSGPRLiveRangesID);
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2013-06-05 21:38:04 +00:00
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}
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2012-12-11 21:25:42 +00:00
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return false;
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}
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bool AMDGPUPassConfig::addPostRegAlloc() {
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2013-01-18 21:15:53 +00:00
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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2014-07-21 16:55:33 +00:00
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addPass(createSIShrinkInstructionsPass());
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2013-06-07 20:37:48 +00:00
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if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
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2013-01-18 21:15:53 +00:00
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addPass(createSIInsertWaits(*TM));
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}
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2012-12-11 21:25:42 +00:00
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return false;
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}
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bool AMDGPUPassConfig::addPreSched2() {
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2013-07-09 15:03:33 +00:00
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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2012-12-11 21:25:42 +00:00
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2013-10-01 19:32:58 +00:00
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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2013-12-11 17:51:41 +00:00
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addPass(createR600EmitClauseMarkers());
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2013-11-18 19:43:33 +00:00
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if (ST.isIfCvtEnabled())
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addPass(&IfConverterID);
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2013-10-01 19:32:58 +00:00
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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addPass(createR600ClauseMergePass(*TM));
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2012-12-11 21:25:42 +00:00
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return false;
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}
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bool AMDGPUPassConfig::addPreEmitPass() {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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2013-06-07 20:37:48 +00:00
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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2013-12-11 17:51:47 +00:00
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addPass(createAMDGPUCFGStructurizerPass());
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2012-12-11 21:25:42 +00:00
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addPass(createR600ExpandSpecialInstrsPass(*TM));
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addPass(&FinalizeMachineBundlesID);
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2013-04-30 00:14:27 +00:00
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addPass(createR600Packetizer(*TM));
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addPass(createR600ControlFlowFinalizer(*TM));
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2012-12-11 21:25:42 +00:00
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} else {
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addPass(createSILowerControlFlowPass(*TM));
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}
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return false;
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}
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