llvm-6502/test/MC/Sparc/sparcv9-atomic-instructions.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s

        ! CHECK: membar 15             ! encoding: [0x81,0x43,0xe0,0x0f]
        membar 15

        ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
        cas [%i0], %l6, %o2

        ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
        casx [%i0], %l6, %o2
Sparc: Add the "alternate address space" load/store instructions. - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237581 91177308-0d34-0410-b5e6-96231b3b80d8 2015-05-18 16:35:04 +00:00			`! RUN: llvm-mc %s -arch=sparcv9 -show-encoding \| FileCheck %s`

			`! CHECK: membar 15 ! encoding: [0x81,0x43,0xe0,0x0f]`
			`membar 15`

			`! CHECK: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]`
			`cas [%i0], %l6, %o2`

			`! CHECK: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]`
			`casx [%i0], %l6, %o2`