2012-02-18 12:03:15 +00:00
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//===-- PPCBranchSelector.cpp - Emit long conditional branches ------------===//
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2005-04-21 23:30:14 +00:00
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//
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2004-07-27 18:33:06 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-07-27 18:33:06 +00:00
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//===----------------------------------------------------------------------===//
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//
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2005-04-21 23:30:14 +00:00
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// This file contains a pass that scans a machine function to determine which
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2004-07-27 18:33:06 +00:00
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// conditional branches need more than 16 bits of displacement to reach their
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// target basic block. It does this in two passes; a calculation of basic block
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2010-08-23 20:30:51 +00:00
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// positions pass, and a branch pseudo op to machine branch opcode pass. This
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2004-07-27 18:33:06 +00:00
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// pass should be run last, just before the assembly printer.
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:51:18 +00:00
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#include "PPC.h"
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2012-12-03 16:50:05 +00:00
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#include "MCTargetDesc/PPCPredicates.h"
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2005-10-14 23:45:43 +00:00
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#include "PPCInstrBuilder.h"
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2005-10-14 23:59:06 +00:00
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#include "PPCInstrInfo.h"
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2006-11-16 18:13:49 +00:00
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#include "llvm/ADT/Statistic.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2006-11-18 00:32:03 +00:00
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#include "llvm/Support/MathExtras.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Target/TargetMachine.h"
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2014-08-04 21:25:23 +00:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2004-07-27 18:33:06 +00:00
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using namespace llvm;
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2014-04-22 02:41:26 +00:00
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#define DEBUG_TYPE "ppc-branch-select"
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2006-12-19 22:59:26 +00:00
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STATISTIC(NumExpanded, "Number of branches expanded to long format");
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2006-11-16 18:13:49 +00:00
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2013-02-13 17:40:07 +00:00
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namespace llvm {
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void initializePPCBSelPass(PassRegistry&);
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}
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2004-07-27 18:33:06 +00:00
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namespace {
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2009-10-25 06:33:48 +00:00
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struct PPCBSel : public MachineFunctionPass {
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2007-05-03 01:11:54 +00:00
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static char ID;
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2013-02-13 17:40:07 +00:00
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PPCBSel() : MachineFunctionPass(ID) {
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initializePPCBSelPass(*PassRegistry::getPassRegistry());
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}
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2007-05-01 21:15:47 +00:00
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2006-11-18 00:32:03 +00:00
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/// BlockSizes - The sizes of the basic blocks in the function.
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std::vector<unsigned> BlockSizes;
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2004-07-27 18:33:06 +00:00
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2014-04-29 07:57:37 +00:00
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bool runOnMachineFunction(MachineFunction &Fn) override;
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2004-07-27 18:33:06 +00:00
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2014-04-29 07:57:37 +00:00
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const char *getPassName() const override {
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2006-11-18 00:32:03 +00:00
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return "PowerPC Branch Selector";
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2004-07-27 18:33:06 +00:00
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}
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};
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2007-05-03 01:11:54 +00:00
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char PPCBSel::ID = 0;
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2004-07-27 18:33:06 +00:00
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}
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2013-02-13 17:40:07 +00:00
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INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
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false, false)
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2004-07-27 18:33:06 +00:00
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/// createPPCBranchSelectionPass - returns an instance of the Branch Selection
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/// Pass
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///
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FunctionPass *llvm::createPPCBranchSelectionPass() {
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2006-02-08 19:33:26 +00:00
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return new PPCBSel();
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}
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bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
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2014-08-05 02:39:49 +00:00
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const PPCInstrInfo *TII =
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static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
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2006-11-18 00:32:03 +00:00
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// Give the blocks of the function a dense, in-order, numbering.
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Fn.RenumberBlocks();
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BlockSizes.resize(Fn.getNumBlockIDs());
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2015-01-03 14:58:25 +00:00
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auto GetAlignmentAdjustment =
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[TII](MachineBasicBlock &MBB, unsigned Offset) -> unsigned {
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unsigned Align = MBB.getAlignment();
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if (!Align)
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return 0;
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unsigned AlignAmt = 1 << Align;
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unsigned ParentAlign = MBB.getParent()->getAlignment();
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if (Align <= ParentAlign)
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return OffsetToAlignment(Offset, AlignAmt);
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// The alignment of this MBB is larger than the function's alignment, so we
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// can't tell whether or not it will insert nops. Assume that it will.
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return AlignAmt + OffsetToAlignment(Offset, AlignAmt);
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};
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2006-11-18 00:32:03 +00:00
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// Measure each MBB and compute a size for the entire function.
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unsigned FuncSize = 0;
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2006-02-08 19:33:26 +00:00
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock *MBB = MFI;
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2006-11-18 00:32:03 +00:00
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2015-01-03 14:58:25 +00:00
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// The end of the previous block may have extra nops if this block has an
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// alignment requirement.
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if (MBB->getNumber() > 0) {
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unsigned AlignExtra = GetAlignmentAdjustment(*MBB, FuncSize);
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BlockSizes[MBB->getNumber()-1] += AlignExtra;
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FuncSize += AlignExtra;
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}
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2006-11-18 00:32:03 +00:00
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unsigned BlockSize = 0;
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2006-02-08 19:33:26 +00:00
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for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
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MBBI != EE; ++MBBI)
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2008-04-16 20:10:13 +00:00
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BlockSize += TII->GetInstSizeInBytes(MBBI);
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2006-11-18 00:32:03 +00:00
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BlockSizes[MBB->getNumber()] = BlockSize;
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FuncSize += BlockSize;
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2006-02-08 19:33:26 +00:00
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}
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2006-11-18 00:32:03 +00:00
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// If the entire function is smaller than the displacement of a branch field,
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// we know we don't need to shrink any branches in this function. This is a
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// common case.
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if (FuncSize < (1 << 15)) {
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BlockSizes.clear();
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return false;
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}
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2006-02-08 19:33:26 +00:00
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2006-11-18 00:32:03 +00:00
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// For each conditional branch, if the offset to its destination is larger
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// than the offset field allows, transform it into a long branch sequence
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// like this:
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// short branch:
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// bCC MBB
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// long branch:
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// b!CC $PC+8
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// b MBB
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2006-02-08 19:33:26 +00:00
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//
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2006-11-18 00:32:03 +00:00
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bool MadeChange = true;
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bool EverMadeChange = false;
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while (MadeChange) {
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// Iteratively expand branches until we reach a fixed point.
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MadeChange = false;
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock &MBB = *MFI;
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unsigned MBBStartOffset = 0;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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2014-04-25 05:30:21 +00:00
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MachineBasicBlock *Dest = nullptr;
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2013-05-21 14:21:09 +00:00
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if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
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Dest = I->getOperand(2).getMBB();
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Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
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else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
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!I->getOperand(1).isImm())
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Dest = I->getOperand(1).getMBB();
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2013-05-21 14:21:09 +00:00
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else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
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I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
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!I->getOperand(0).isImm())
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Dest = I->getOperand(0).getMBB();
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if (!Dest) {
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2008-04-16 20:10:13 +00:00
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MBBStartOffset += TII->GetInstSizeInBytes(I);
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2006-11-18 00:32:03 +00:00
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continue;
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}
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// Determine the offset from the current branch to the destination
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// block.
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int BranchSize;
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if (Dest->getNumber() <= MBB.getNumber()) {
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// If this is a backwards branch, the delta is the offset from the
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// start of this block to this branch, plus the sizes of all blocks
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// from this block to the dest.
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BranchSize = MBBStartOffset;
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for (unsigned i = Dest->getNumber(), e = MBB.getNumber(); i != e; ++i)
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BranchSize += BlockSizes[i];
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} else {
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// Otherwise, add the size of the blocks between this block and the
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// dest to the number of bytes left in this block.
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BranchSize = -MBBStartOffset;
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for (unsigned i = MBB.getNumber(), e = Dest->getNumber(); i != e; ++i)
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BranchSize += BlockSizes[i];
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}
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2006-11-17 22:10:59 +00:00
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2006-11-18 00:32:03 +00:00
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// If this branch is in range, ignore it.
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2010-03-29 21:13:41 +00:00
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if (isInt<16>(BranchSize)) {
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2006-11-18 00:32:03 +00:00
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MBBStartOffset += 4;
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continue;
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}
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2012-06-08 15:38:21 +00:00
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2006-11-18 00:32:03 +00:00
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// Otherwise, we have to expand it to a long branch.
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MachineInstr *OldBranch = I;
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2009-02-13 02:27:39 +00:00
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DebugLoc dl = OldBranch->getDebugLoc();
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2012-06-08 15:38:21 +00:00
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if (I->getOpcode() == PPC::BCC) {
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// The BCC operands are:
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// 0. PPC branch predicate
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// 1. CR register
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// 2. Target MBB
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PPC::Predicate Pred = (PPC::Predicate)I->getOperand(0).getImm();
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unsigned CRReg = I->getOperand(1).getReg();
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// Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
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BuildMI(MBB, I, dl, TII->get(PPC::BCC))
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.addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
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Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
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} else if (I->getOpcode() == PPC::BC) {
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unsigned CRBit = I->getOperand(0).getReg();
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BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
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} else if (I->getOpcode() == PPC::BCn) {
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unsigned CRBit = I->getOperand(0).getReg();
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BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
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2012-06-08 15:38:21 +00:00
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} else if (I->getOpcode() == PPC::BDNZ) {
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BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
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} else if (I->getOpcode() == PPC::BDNZ8) {
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BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
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} else if (I->getOpcode() == PPC::BDZ) {
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BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
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} else if (I->getOpcode() == PPC::BDZ8) {
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BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
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} else {
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llvm_unreachable("Unhandled branch type!");
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}
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2006-11-18 00:32:03 +00:00
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// Uncond branch to the real destination.
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2009-02-13 02:27:39 +00:00
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I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
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2006-11-18 00:32:03 +00:00
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// Remove the old branch from the function.
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OldBranch->eraseFromParent();
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// Remember that this instruction is 8-bytes, increase the size of the
|
|
|
|
// block by 4, remember to iterate.
|
|
|
|
BlockSizes[MBB.getNumber()] += 4;
|
|
|
|
MBBStartOffset += 8;
|
2006-11-16 23:49:52 +00:00
|
|
|
++NumExpanded;
|
2006-11-18 00:32:03 +00:00
|
|
|
MadeChange = true;
|
2006-11-16 23:49:52 +00:00
|
|
|
}
|
2006-02-08 19:33:26 +00:00
|
|
|
}
|
2006-11-18 00:32:03 +00:00
|
|
|
EverMadeChange |= MadeChange;
|
2006-02-08 19:33:26 +00:00
|
|
|
}
|
|
|
|
|
2006-11-18 00:32:03 +00:00
|
|
|
BlockSizes.clear();
|
2006-02-08 19:33:26 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|