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llvm-6502/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll

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Revert the test moves from 176733. Use "REQUIRES: asserts" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12 16:27:52 +00:00
; REQUIRES: asserts
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 13:19:42 +00:00
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats 2>&1 | grep "4 machine-licm"
Add mcpu to tests to prevent them from using AVX instructions on Sandy Bridge after r155618. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 07:11:58 +00:00
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn | FileCheck %s
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 00:02:22 +00:00
; rdar://6627786
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-26 00:07:25 +00:00
; rdar://7792037
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 00:02:22 +00:00
target triple = "x86_64-apple-darwin10.0"
%struct.Key = type { i64 }
%struct.__Rec = type opaque
%struct.__vv = type { }
Make this test less trivial, to avoid spurious failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 17:23:56 +00:00
define %struct.__vv* @t(%struct.Key* %desc, i64 %p) nounwind ssp {
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 00:02:22 +00:00
entry:
br label %bb4
bb4: ; preds = %bb.i, %bb26, %bb4, %entry
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-26 00:07:25 +00:00
; CHECK: %bb4
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 13:19:42 +00:00
; CHECK: xorl
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-26 00:07:25 +00:00
; CHECK: callq
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:48:58 +00:00
; CHECK: movq
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-26 00:07:25 +00:00
; CHECK: xorl
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30 13:19:42 +00:00
; CHECK: xorl
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-26 00:07:25 +00:00
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 00:02:22 +00:00
%0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0]
Make this test less trivial, to avoid spurious failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 17:23:56 +00:00
%ins = or i64 %p, 2097152 ; <i64> [#uses=1]
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 00:02:22 +00:00
%1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1]
%cond = icmp eq i32 %1, 1 ; <i1> [#uses=1]
br i1 %cond, label %bb26, label %bb4
bb26: ; preds = %bb4
%2 = and i64 %ins, 15728640 ; <i64> [#uses=1]
%cond.i = icmp eq i64 %2, 1048576 ; <i1> [#uses=1]
br i1 %cond.i, label %bb.i, label %bb4
bb.i: ; preds = %bb26
%3 = load i32* null, align 4 ; <i32> [#uses=1]
%4 = uitofp i32 %3 to float ; <float> [#uses=1]
%.sum13.i = add i64 0, 4 ; <i64> [#uses=1]
%5 = getelementptr i8* null, i64 %.sum13.i ; <i8*> [#uses=1]
%6 = bitcast i8* %5 to i32* ; <i32*> [#uses=1]
%7 = load i32* %6, align 4 ; <i32> [#uses=1]
%8 = uitofp i32 %7 to float ; <float> [#uses=1]
%.sum.i = add i64 0, 8 ; <i64> [#uses=1]
%9 = getelementptr i8* null, i64 %.sum.i ; <i8*> [#uses=1]
%10 = bitcast i8* %9 to i32* ; <i32*> [#uses=1]
%11 = load i32* %10, align 4 ; <i32> [#uses=1]
%12 = uitofp i32 %11 to float ; <float> [#uses=1]
%13 = insertelement <4 x float> undef, float %4, i32 0 ; <<4 x float>> [#uses=1]
%14 = insertelement <4 x float> %13, float %8, i32 1 ; <<4 x float>> [#uses=1]
%15 = insertelement <4 x float> %14, float %12, i32 2 ; <<4 x float>> [#uses=1]
store <4 x float> %15, <4 x float>* null, align 16
br label %bb4
}
declare i32 @xxGetOffsetForCode(...)
declare i32 @xxCalculateMidType(...)
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