6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-06-30 23:30:28 +00:00
Code Issues Projects Releases Wiki Activity

Add mcpu to tests to prevent them from using AVX instructions on Sandy Bridge after r155618.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155696 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-04-27 07:11:58 +00:00
parent afb3b5ebe6
commit 76c5897eae
32 changed files with 49 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test/CodeGen/X86/2006-05-11-InstrSched.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+sse2 -stats -realign-stack=0 |&\
; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=+sse2 -stats -realign-stack=0 |&\
; RUN: grep {asm-printer} | grep 35
target datalayout = "e-p:32:32"

4
test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -stats |& grep {8 machine-licm}
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats |& grep {8 machine-licm}
; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn | FileCheck %s
; rdar://6627786
; rdar://7792037

4
test/CodeGen/X86/2011-12-15-vec_shift.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=x86-64 -mattr=+sse41 < %s | FileCheck %s -check-prefix=CHECK-W-SSE4
; RUN: llc -march=x86-64 -mattr=-sse41 < %s | FileCheck %s -check-prefix=CHECK-WO-SSE4
; RUN: llc -march=x86-64 -mattr=+sse41 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-W-SSE4
; RUN: llc -march=x86-64 -mattr=-sse41 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-WO-SSE4
; Test case for r146671
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.7"

4
test/CodeGen/X86/break-sse-dep.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -mcpu=nehalem | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 -mcpu=nehalem | FileCheck %s
define double @t1(float* nocapture %x) nounwind readonly ssp {
entry:

4
test/CodeGen/X86/gather-addresses.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-win32 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-linux -mcpu=nehalem < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s
; rdar://7398554
; When doing vector gather-scatter index calculation with 32-bit indices,

8
test/CodeGen/X86/illegal-vector-args-return.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {mulpd %xmm3, %xmm1}
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {mulpd %xmm2, %xmm0}
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {addps %xmm3, %xmm1}
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {addps %xmm2, %xmm0}
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep {mulpd %xmm3, %xmm1}
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep {mulpd %xmm2, %xmm0}
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep {addps %xmm3, %xmm1}
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=nehalem | grep {addps %xmm2, %xmm0}
define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
%y = fmul <4 x double> %x, %z

4
test/CodeGen/X86/lsr-reuse-trunc.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=nehalem | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=nehalem | FileCheck %s
; Full strength reduction wouldn't reduce register pressure, so LSR should
; stick with indexing here.

2
test/CodeGen/X86/multiple-loop-post-inc.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 < %s | FileCheck %s
; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s
; rdar://7236213
; Xfailed now that scheduler 2-address hack is disabled a lea is generated.

2
test/CodeGen/X86/pmul.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 -join-physregs > %t
; RUN: llc < %s -march=x86 -mattr=sse41 -mcpu=nehalem -stack-alignment=16 -join-physregs > %t
; RUN: grep pmul %t | count 12
; RUN: grep mov %t | count 11

2
test/CodeGen/X86/sink-hoist.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s
; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true | FileCheck %s
; Currently, floating-point selects are lowered to CFG triangles.
; This means that one side of the select is always unconditionally

2
test/CodeGen/X86/splat-scalar-load.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | FileCheck %s
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -mcpu=nehalem | FileCheck %s
; rdar://7434544
define <2 x i64> @t2() nounwind {

2
test/CodeGen/X86/sse-align-12.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=nehalem | FileCheck %s
; CHECK: a:
; CHECK: movdqu

2
test/CodeGen/X86/sse-domains.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc < %s -mcpu=nehalem | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.7"

6
test/CodeGen/X86/sse-minmax.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -promote-elements | FileCheck %s
; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s
; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=FINITE %s
; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -join-physregs -promote-elements | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s
; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -join-physregs -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=FINITE %s
; Some of these patterns can be matched as SSE min or max. Some of
; then can be matched provided that the operands are swapped.

4
test/CodeGen/X86/sse41.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse41 -mcpu=penryn | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse41 -mcpu=penryn | FileCheck %s -check-prefix=X64
@g16 = external global i16

2
test/CodeGen/X86/twoaddr-coalesce-2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& \
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -stats |& \
; RUN: grep {twoaddrinstr} | grep {Number of instructions aggressively commuted}
; rdar://6480363

4
test/CodeGen/X86/vec_insert-6.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pslldq
; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 6
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn | grep pslldq
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -mtriple=i686-apple-darwin9 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 6
define <4 x float> @t3(<4 x float>* %P) nounwind {
%tmp1 = load <4 x float>* %P

2
test/CodeGen/X86/vec_set-3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -o %t
; RUN: grep pshufd %t | count 2
define <4 x float> @test(float %a) nounwind {

4
test/CodeGen/X86/vec_shuffle-16.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse
; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
; sse: t1:
; sse2: t1:

2
test/CodeGen/X86/vec_shuffle-19.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -o /dev/null -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4
; RUN: llc < %s -o /dev/null -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4
; PR2485
define <4 x i32> @t(<4 x i32> %a, <4 x i32> %b) nounwind {

4
test/CodeGen/X86/vec_shuffle-27.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=sse41 | FileCheck %s
; ModuleID = 'vec_shuffle-27.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
@ -35,4 +35,4 @@ entry:
store <4 x i64> %vect1487, <4 x i64>* %ap
store <4 x i64> %vect1488, <4 x i64>* %bp
ret void;
}
}

2
test/CodeGen/X86/vec_shuffle-36.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=penryn -mattr=sse41 | FileCheck %s
define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
; CHECK: pshufb

4
test/CodeGen/X86/vec_shuffle-37.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=core2 | FileCheck %s
; RUN: llc -O0 < %s -march=x86 -mcpu=core2 | FileCheck %s --check-prefix=CHECK_O0
define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp {

2
test/CodeGen/X86/vec_shuffle-39.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn | FileCheck %s
; rdar://10050222, rdar://10134392
define <4 x float> @t1(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {

2
test/CodeGen/X86/vec_splat-2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd | count 1
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 | grep pshufd | count 1
define void @test(<2 x i64>* %P, i8 %x) nounwind {
%tmp = insertelement <16 x i8> zeroinitializer, i8 %x, i32 0 ; <<16 x i8>> [#uses=1]

2
test/CodeGen/X86/vec_splat-3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=sse41 -o %t
; RUN: grep punpcklwd %t | count 4
; RUN: grep punpckhwd %t | count 4
; RUN: grep "pshufd" %t | count 8

2
test/CodeGen/X86/vec_splat-4.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=sse41 -o %t
; RUN: grep punpcklbw %t | count 16
; RUN: grep punpckhbw %t | count 16
; RUN: grep "pshufd" %t | count 16

4
test/CodeGen/X86/vec_splat.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd
; RUN: llc < %s -march=x86 -mattr=+sse3 | grep movddup
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 | grep pshufd
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse3 | grep movddup
define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind {
%tmp = insertelement <4 x float> zeroinitializer, float %X, i32 0 ; <<4 x float>> [#uses=1]

2
test/CodeGen/X86/widen_cast-2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; CHECK: pextrd
; CHECK: pextrd
; CHECK: movd

2
test/CodeGen/X86/widen_conv-4.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; CHECK-NOT: cvtsi2ss
; unsigned to float v7i16 to v7f32

2
test/CodeGen/X86/widen_extract-1.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; widen extract subvector
define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {

4
test/CodeGen/X86/x86-64-dead-stack-adjust.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s | not grep rsp
; RUN: llc < %s | grep cvttsd2siq
; RUN: llc < %s -mcpu=nehalem | not grep rsp
; RUN: llc < %s -mcpu=nehalem | grep cvttsd2siq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"