I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This defines functionality used to emit comments about X86 instructions to
|
|
|
|
// an output stream for -fverbose-asm.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "X86InstComments.h"
|
2011-07-06 22:01:53 +00:00
|
|
|
#include "MCTargetDesc/X86MCTargetDesc.h"
|
2011-07-26 00:24:13 +00:00
|
|
|
#include "Utils/X86ShuffleDecode.h"
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
#include "llvm/MC/MCInst.h"
|
2014-03-15 09:11:41 +00:00
|
|
|
#include "llvm/CodeGen/MachineValueType.h"
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2014-03-12 08:00:24 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
using namespace llvm;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Top Level Entrypoint
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
|
|
|
|
/// newline terminated strings to the specified string if desired. This
|
|
|
|
/// information is shown in disassembly dumps when verbose assembly is enabled.
|
|
|
|
void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
|
|
|
|
const char *(*getRegName)(unsigned)) {
|
|
|
|
// If this is a shuffle operation, the switch should fill in this state.
|
2012-03-20 06:42:26 +00:00
|
|
|
SmallVector<int, 8> ShuffleMask;
|
2014-04-25 05:30:21 +00:00
|
|
|
const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
case X86::INSERTPSrr:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VINSERTPSrr:
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(3).isImm())
|
|
|
|
DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::MOVLHPSrr:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VMOVLHPSrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeMOVLHPSMask(2, ShuffleMask);
|
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::MOVHLPSrr:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VMOVHLPSrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeMOVHLPSMask(2, ShuffleMask);
|
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2013-01-26 13:31:37 +00:00
|
|
|
case X86::PALIGNR128rr:
|
|
|
|
case X86::VPALIGNR128rr:
|
|
|
|
Src1Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::PALIGNR128rm:
|
|
|
|
case X86::VPALIGNR128rm:
|
|
|
|
Src2Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePALIGNRMask(MVT::v16i8,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2013-01-26 13:31:37 +00:00
|
|
|
break;
|
|
|
|
case X86::VPALIGNR256rr:
|
|
|
|
Src1Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPALIGNR256rm:
|
|
|
|
Src2Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePALIGNRMask(MVT::v32i8,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2013-01-28 07:19:11 +00:00
|
|
|
break;
|
2013-01-26 13:31:37 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
case X86::PSHUFDri:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VPSHUFDri:
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::PSHUFDmi:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VPSHUFDmi:
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFMask(MVT::v4i32,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2012-02-06 07:17:51 +00:00
|
|
|
break;
|
|
|
|
case X86::VPSHUFDYri:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPSHUFDYmi:
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFMask(MVT::v8i32,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2012-02-06 07:17:51 +00:00
|
|
|
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::PSHUFHWri:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VPSHUFHWri:
|
2010-08-29 03:08:08 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::PSHUFHWmi:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VPSHUFHWmi:
|
2010-08-29 03:08:08 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFHWMask(MVT::v8i16,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2012-05-02 08:03:44 +00:00
|
|
|
break;
|
|
|
|
case X86::VPSHUFHWYri:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPSHUFHWYmi:
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFHWMask(MVT::v16i16,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PSHUFLWri:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VPSHUFLWri:
|
2010-08-29 03:08:08 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::PSHUFLWmi:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VPSHUFLWmi:
|
2010-08-29 03:08:08 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFLWMask(MVT::v8i16,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2012-05-02 08:03:44 +00:00
|
|
|
break;
|
|
|
|
case X86::VPSHUFLWYri:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPSHUFLWYmi:
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFLWMask(MVT::v16i16,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::PUNPCKHBWrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHBWrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKHBWrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHBWrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKHBWYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKHBWYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v32i8, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PUNPCKHWDrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHWDrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKHWDrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHWDrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v8i16, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKHWDYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKHWDYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v16i16, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PUNPCKHDQrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHDQrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKHDQrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHDQrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKHDQYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKHDQYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v8i32, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PUNPCKHQDQrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHQDQrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKHQDQrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKHQDQrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v2i64, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKHQDQYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKHQDQYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKHMask(MVT::v4i64, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::PUNPCKLBWrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLBWrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKLBWrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLBWrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKLBWYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKLBWYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v32i8, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PUNPCKLWDrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLWDrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKLWDrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLWDrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v8i16, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKLWDYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKLWDYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v16i16, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PUNPCKLDQrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLDQrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKLDQrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLDQrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKLDQYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKLDQYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v8i32, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
|
|
|
case X86::PUNPCKLQDQrr:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLQDQrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::PUNPCKLQDQrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
case X86::VPUNPCKLQDQrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v2i64, ShuffleMask);
|
|
|
|
break;
|
|
|
|
case X86::VPUNPCKLQDQYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPUNPCKLQDQYrm:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
DecodeUNPCKLMask(MVT::v4i64, ShuffleMask);
|
2010-08-29 03:08:08 +00:00
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
case X86::SHUFPDrri:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VSHUFPDrri:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::SHUFPDrmi:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VSHUFPDrmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodeSHUFPMask(MVT::v2f64,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
break;
|
|
|
|
case X86::VSHUFPDYrri:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VSHUFPDYrmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodeSHUFPMask(MVT::v4f64,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-22 14:27:57 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
case X86::SHUFPSrri:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VSHUFPSrri:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::SHUFPSrmi:
|
2011-11-22 14:27:57 +00:00
|
|
|
case X86::VSHUFPSrmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodeSHUFPMask(MVT::v4f32,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
break;
|
|
|
|
case X86::VSHUFPSYrri:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VSHUFPSYrmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodeSHUFPMask(MVT::v8f32,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-22 14:27:57 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
break;
|
2010-09-02 18:40:13 +00:00
|
|
|
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::UNPCKLPDrr:
|
2011-02-28 19:06:56 +00:00
|
|
|
case X86::VUNPCKLPDrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::UNPCKLPDrm:
|
2011-02-28 19:06:56 +00:00
|
|
|
case X86::VUNPCKLPDrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKLMask(MVT::v2f64, ShuffleMask);
|
2011-02-28 19:06:56 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-02-28 19:06:56 +00:00
|
|
|
break;
|
|
|
|
case X86::VUNPCKLPDYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VUNPCKLPDYrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKLMask(MVT::v4f64, ShuffleMask);
|
2011-02-28 19:06:56 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-02-28 19:06:56 +00:00
|
|
|
break;
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
case X86::UNPCKLPSrr:
|
2011-02-28 19:06:56 +00:00
|
|
|
case X86::VUNPCKLPSrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::UNPCKLPSrm:
|
2011-02-28 19:06:56 +00:00
|
|
|
case X86::VUNPCKLPSrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKLMask(MVT::v4f32, ShuffleMask);
|
2011-02-28 19:06:56 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-02-28 19:06:56 +00:00
|
|
|
break;
|
|
|
|
case X86::VUNPCKLPSYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VUNPCKLPSYrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKLMask(MVT::v8f32, ShuffleMask);
|
2011-02-28 19:06:56 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-02-28 19:06:56 +00:00
|
|
|
break;
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::UNPCKHPDrr:
|
2011-11-22 01:57:35 +00:00
|
|
|
case X86::VUNPCKHPDrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::UNPCKHPDrm:
|
2011-11-22 01:57:35 +00:00
|
|
|
case X86::VUNPCKHPDrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKHMask(MVT::v2f64, ShuffleMask);
|
2011-11-22 01:57:35 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-11-22 01:57:35 +00:00
|
|
|
break;
|
|
|
|
case X86::VUNPCKHPDYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VUNPCKHPDYrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKHMask(MVT::v4f64, ShuffleMask);
|
2011-11-22 01:57:35 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-11-22 01:57:35 +00:00
|
|
|
break;
|
2010-08-29 03:08:08 +00:00
|
|
|
case X86::UNPCKHPSrr:
|
2011-11-22 01:57:35 +00:00
|
|
|
case X86::VUNPCKHPSrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
2013-01-29 07:54:31 +00:00
|
|
|
case X86::UNPCKHPSrm:
|
2011-11-22 01:57:35 +00:00
|
|
|
case X86::VUNPCKHPSrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKHMask(MVT::v4f32, ShuffleMask);
|
2011-11-22 01:57:35 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-11-22 01:57:35 +00:00
|
|
|
break;
|
|
|
|
case X86::VUNPCKHPSYrr:
|
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VUNPCKHPSYrm:
|
2011-12-06 05:31:16 +00:00
|
|
|
DecodeUNPCKHMask(MVT::v8f32, ShuffleMask);
|
2011-11-22 01:57:35 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
2011-11-22 14:27:57 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-11-22 01:57:35 +00:00
|
|
|
break;
|
2011-07-29 01:31:11 +00:00
|
|
|
case X86::VPERMILPSri:
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPERMILPSmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFMask(MVT::v4f32,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-08-04 15:45:59 +00:00
|
|
|
break;
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
case X86::VPERMILPSYri:
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPERMILPSYmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFMask(MVT::v8f32,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
break;
|
2011-07-29 01:31:11 +00:00
|
|
|
case X86::VPERMILPDri:
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPERMILPDmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFMask(MVT::v2f64,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-07-29 01:31:11 +00:00
|
|
|
break;
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
case X86::VPERMILPDYri:
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPERMILPDYmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodePSHUFMask(MVT::v4f64,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
break;
|
2011-08-12 21:48:26 +00:00
|
|
|
case X86::VPERM2F128rr:
|
2011-11-29 07:49:05 +00:00
|
|
|
case X86::VPERM2I128rr:
|
2011-08-12 21:48:26 +00:00
|
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
2011-11-29 07:49:05 +00:00
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPERM2F128rm:
|
|
|
|
case X86::VPERM2I128rm:
|
2012-02-06 07:17:51 +00:00
|
|
|
// For instruction comments purpose, assume the 256-bit vector is v4i64.
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodeVPERM2X128Mask(MVT::v4i64,
|
|
|
|
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2011-11-29 07:49:05 +00:00
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
2011-08-12 21:48:26 +00:00
|
|
|
break;
|
2012-05-06 18:44:02 +00:00
|
|
|
case X86::VPERMQYri:
|
|
|
|
case X86::VPERMPDYri:
|
|
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
|
|
// FALL THROUGH.
|
|
|
|
case X86::VPERMQYmi:
|
|
|
|
case X86::VPERMPDYmi:
|
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand
is an immediate and has not been symbolicated to MCExpr operand.
I’m trying to enable the ‘C’ disassembly API option
LLVMDisassembler_Option_SetInstrComments for darwin’s
otool(1) that uses the llvm disassembler API. The problem is
that the disassembler API can change an immediate operand to
an MCExpr operand if it symbolicates it with the call backs.
And if it does the code in llvm::EmitAnyX86InstComments()
will crash when it assumes these operands are immediates.
The fix for this is very straight forward to just protect the call
to getImm() with a check of isImm(). So if the immediate for
an instruction is symbolicated it simply doesn’t get the X86
verbose assembly comments:
% otool -tV test_asm.o
test_asm.o:
(__TEXT,__text) section
_t1:
0000000000000000 vpshufd $_t1, %xmm1, %xmm0
0000000000000005 retq
0000000000000006 nopw %cs:_t1(%rax,%rax)
_t2:
0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3]
0000000000000015 retq
0000000000000016 nopw %cs:_t1(%rax,%rax)
_t3:
0000000000000020 vpshufd $_t1, %xmm1, %xmm0
0000000000000025 retq
0000000000000026 nopw %cs:_t1(%rax,%rax)
_t4:
0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0]
0000000000000035 retq
The fact that the immediate $0x0 is being symbolicated at
all in this case is a different problem which my next patch
will address.
rdar://10989286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 00:18:51 +00:00
|
|
|
if(MI->getOperand(MI->getNumOperands()-1).isImm())
|
|
|
|
DecodeVPERMMask(MI->getOperand(MI->getNumOperands()-1).getImm(),
|
|
|
|
ShuffleMask);
|
2012-05-06 18:44:02 +00:00
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
|
|
break;
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
}
|
|
|
|
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
// If this was a shuffle operation, print the shuffle mask.
|
|
|
|
if (!ShuffleMask.empty()) {
|
2014-04-25 05:30:21 +00:00
|
|
|
if (!DestName) DestName = Src1Name;
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
OS << (DestName ? DestName : "mem") << " = ";
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
// If the two sources are the same, canonicalize the input elements to be
|
|
|
|
// from the first src so that we get larger element spans.
|
|
|
|
if (Src1Name == Src2Name) {
|
|
|
|
for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
|
|
|
|
if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
|
2012-03-20 06:42:26 +00:00
|
|
|
ShuffleMask[i] >= (int)e) // From second mask.
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
ShuffleMask[i] -= e;
|
|
|
|
}
|
|
|
|
}
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
// The shuffle mask specifies which elements of the src1/src2 fill in the
|
|
|
|
// destination, with a few sentinel values. Loop through and print them
|
|
|
|
// out.
|
|
|
|
for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
|
|
|
|
if (i != 0)
|
|
|
|
OS << ',';
|
2012-03-21 13:48:11 +00:00
|
|
|
if (ShuffleMask[i] == SM_SentinelZero) {
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
OS << "zero";
|
|
|
|
continue;
|
|
|
|
}
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
// Otherwise, it must come from src1 or src2. Print the span of elements
|
|
|
|
// that comes from this src.
|
2012-03-20 06:42:26 +00:00
|
|
|
bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
const char *SrcName = isSrc1 ? Src1Name : Src2Name;
|
|
|
|
OS << (SrcName ? SrcName : "mem") << '[';
|
|
|
|
bool IsFirst = true;
|
|
|
|
while (i != e &&
|
|
|
|
(int)ShuffleMask[i] >= 0 &&
|
2012-03-20 06:42:26 +00:00
|
|
|
(ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
if (!IsFirst)
|
|
|
|
OS << ',';
|
|
|
|
else
|
|
|
|
IsFirst = false;
|
|
|
|
OS << ShuffleMask[i] % ShuffleMask.size();
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
OS << ']';
|
|
|
|
--i; // For loop increments element #.
|
|
|
|
}
|
|
|
|
//MI->print(OS, 0);
|
|
|
|
OS << "\n";
|
|
|
|
}
|
2010-09-02 18:40:13 +00:00
|
|
|
|
I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:42:31 +00:00
|
|
|
}
|