2012-08-24 18:14:27 +00:00
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; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
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2014-05-30 10:56:12 +00:00
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; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
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; XFAIL: arm,aarch64
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2012-08-24 18:14:27 +00:00
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; Make sure we have the correct weight attached to each successor.
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define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
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; CHECK: Machine code for function test2:
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entry:
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%conv = sext i32 %x to i64
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switch i64 %conv, label %return [
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i64 0, label %sw.bb
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i64 1, label %sw.bb
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i64 4, label %sw.bb
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i64 5, label %sw.bb1
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], !prof !0
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; CHECK: BB#0: derived from LLVM BB %entry
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; CHECK: Successors according to CFG: BB#2(64) BB#4(14)
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; CHECK: BB#4: derived from LLVM BB %entry
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; CHECK: Successors according to CFG: BB#1(10) BB#5(4)
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; CHECK: BB#5: derived from LLVM BB %entry
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; CHECK: Successors according to CFG: BB#1(4) BB#3(7)
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sw.bb:
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br label %return
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sw.bb1:
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br label %return
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return:
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%retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
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ret i32 %retval.0
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}
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!0 = metadata !{metadata !"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
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