llvm-6502/test/CodeGen
Michael Kuperstein 299e0d4c24 [X86] Break false dependencies before partial register updates when the source operand is in memory
Adds the various "rm" instruction variants into the list of instructions that have a partial register update. Also adds all variants of SQRTSD that were missing in the original list.

Differential Revision: http://reviews.llvm.org/D6620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224246 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-15 13:18:21 +00:00
..
AArch64
ARM Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores." 2014-12-13 23:22:12 +00:00
CPP
Generic Rename argument strings of codegen passes to avoid collisions with command line 2014-12-13 04:52:04 +00:00
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC [PowerPC] Handle cmp op promotion for SELECT[_CC] nodes in PPCTL::DAGCombineExtBoolTrunc 2014-12-14 05:53:19 +00:00
R600
SPARC
SystemZ
Thumb
Thumb2 [ARMConstantIsland] Insert tbb/tbh optimization where previous jump table resided. 2014-12-12 23:27:40 +00:00
X86 [X86] Break false dependencies before partial register updates when the source operand is in memory 2014-12-15 13:18:21 +00:00
XCore