2008-05-14 10:17:11 +00:00
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//==-llvm/CodeGen/DAGISelHeader.h - Common DAG ISel definitions -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides definitions of the common, target-independent methods and
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// data, which is used by SelectionDAG-based instruction selectors.
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//
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// *** NOTE: This file is #included into the middle of the target
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2008-10-28 18:47:37 +00:00
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// instruction selector class. These functions are really methods.
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// This is a little awkward, but it allows this code to be shared
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// by all the targets while still being able to call into
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// target-specific code without using a virtual function call.
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//
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2008-05-14 10:17:11 +00:00
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_DAGISEL_HEADER_H
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#define LLVM_CODEGEN_DAGISEL_HEADER_H
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Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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/// ISelPosition - Node iterator marking the current position of
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/// instruction selection as it procedes through the topologically-sorted
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/// node list.
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SelectionDAG::allnodes_iterator ISelPosition;
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2008-05-14 10:17:11 +00:00
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/// IsChainCompatible - Returns true if Chain is Op or Chain does
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/// not reach Op.
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static bool IsChainCompatible(SDNode *Chain, SDNode *Op) {
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if (Chain->getOpcode() == ISD::EntryToken)
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return true;
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2009-01-28 18:03:09 +00:00
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if (Chain->getOpcode() == ISD::TokenFactor)
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2008-05-14 10:17:11 +00:00
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return false;
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2009-01-28 18:03:09 +00:00
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if (Chain->getNumOperands() > 0) {
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2008-07-27 21:46:04 +00:00
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SDValue C0 = Chain->getOperand(0);
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2009-08-11 20:47:22 +00:00
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if (C0.getValueType() == MVT::Other)
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2008-08-28 21:40:38 +00:00
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return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
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2008-05-14 10:17:11 +00:00
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}
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return true;
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}
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Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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/// ISelUpdater - helper class to handle updates of the
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/// instruciton selection graph.
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class VISIBILITY_HIDDEN ISelUpdater : public SelectionDAG::DAGUpdateListener {
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SelectionDAG::allnodes_iterator &ISelPosition;
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public:
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explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
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: ISelPosition(isp) {}
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2008-11-05 17:13:57 +00:00
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/// NodeDeleted - Handle nodes deleted from the graph. If the
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/// node being deleted is the current ISelPosition node, update
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/// ISelPosition.
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///
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Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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virtual void NodeDeleted(SDNode *N, SDNode *E) {
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if (ISelPosition == SelectionDAG::allnodes_iterator(N))
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++ISelPosition;
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2008-05-14 10:17:11 +00:00
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}
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Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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/// NodeUpdated - Ignore updates for now.
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virtual void NodeUpdated(SDNode *N) {}
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};
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2008-05-14 10:17:11 +00:00
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/// ReplaceUses - replace all uses of the old node F with the use
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/// of the new node T.
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2009-11-14 16:37:18 +00:00
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DISABLE_INLINE void ReplaceUses(SDValue F, SDValue T) {
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Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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ISelUpdater ISU(ISelPosition);
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CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
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2008-05-14 10:17:11 +00:00
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}
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2008-07-17 19:10:17 +00:00
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/// ReplaceUses - replace all uses of the old nodes F with the use
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/// of the new nodes T.
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2009-11-14 16:37:18 +00:00
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DISABLE_INLINE void ReplaceUses(const SDValue *F, const SDValue *T,
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unsigned Num) {
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Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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ISelUpdater ISU(ISelPosition);
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CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
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2008-07-17 19:10:17 +00:00
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}
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2008-05-14 10:17:11 +00:00
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/// ReplaceUses - replace all uses of the old node F with the use
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/// of the new node T.
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2009-11-14 16:37:18 +00:00
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DISABLE_INLINE void ReplaceUses(SDNode *F, SDNode *T) {
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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ISelUpdater ISU(ISelPosition);
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2009-04-15 20:06:30 +00:00
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CurDAG->ReplaceAllUsesWith(F, T, &ISU);
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2008-05-14 10:17:11 +00:00
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}
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/// SelectRoot - Top level entry to DAG instruction selector.
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/// Selects instructions starting at the root of the current DAG.
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2008-10-27 21:56:29 +00:00
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void SelectRoot(SelectionDAG &DAG) {
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2008-05-14 10:17:11 +00:00
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SelectRootInit();
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// Create a dummy node (which is not added to allnodes), that adds
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// a reference to the root node, preventing it from being deleted,
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// and tracking any changes of the root.
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HandleSDNode Dummy(CurDAG->getRoot());
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2009-12-03 00:50:42 +00:00
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ISelPosition = llvm::next(SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()));
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2008-05-14 10:17:11 +00:00
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2008-11-05 17:13:57 +00:00
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// The AllNodes list is now topological-sorted. Visit the
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// nodes by starting at the end of the list (the root of the
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// graph) and preceding back toward the beginning (the entry
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// node).
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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while (ISelPosition != CurDAG->allnodes_begin()) {
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SDNode *Node = --ISelPosition;
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2008-11-05 22:56:47 +00:00
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// Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
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// but there are currently some corner cases that it misses. Also, this
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// makes it theoretically possible to disable the DAGCombiner.
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if (Node->use_empty())
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continue;
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2008-10-31 16:12:56 +00:00
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#if 0
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2008-10-27 21:56:29 +00:00
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DAG.setSubgraphColor(Node, "red");
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2008-10-28 17:23:13 +00:00
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#endif
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2010-01-05 01:24:18 +00:00
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SDNode *ResNode = Select(Node);
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2009-12-13 01:00:59 +00:00
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// If node should not be replaced, continue with the next one.
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2008-05-14 10:17:11 +00:00
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if (ResNode == Node)
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continue;
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// Replace node.
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2008-10-27 21:56:29 +00:00
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if (ResNode) {
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2008-10-31 16:12:56 +00:00
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#if 0
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2008-10-27 21:56:29 +00:00
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DAG.setSubgraphColor(ResNode, "yellow");
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DAG.setSubgraphColor(ResNode, "black");
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2008-10-28 17:23:13 +00:00
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#endif
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2008-05-14 10:17:11 +00:00
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ReplaceUses(Node, ResNode);
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2008-10-27 21:56:29 +00:00
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}
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2008-05-14 10:17:11 +00:00
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// If after the replacement this node is not used any more,
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// remove this dead node.
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if (Node->use_empty()) { // Don't delete EntryToken, etc.
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
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ISelUpdater ISU(ISelPosition);
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CurDAG->RemoveDeadNode(Node, &ISU);
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2008-05-14 10:17:11 +00:00
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}
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}
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2008-08-21 16:36:34 +00:00
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CurDAG->setRoot(Dummy.getValue());
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2008-05-14 10:17:11 +00:00
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}
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2010-02-15 08:04:42 +00:00
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/// CheckInteger - Return true if the specified node is not a ConstantSDNode or
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/// if it doesn't have the specified value.
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static bool CheckInteger(SDValue V, int64_t Val) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
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return C == 0 || C->getSExtValue() != Val;
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}
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/// CheckAndImmediate - Check to see if the specified node is an and with an
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/// immediate returning true on failure.
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///
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/// FIXME: Inline this gunk into CheckAndMask.
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bool CheckAndImmediate(SDValue V, int64_t Val) {
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if (V->getOpcode() == ISD::AND)
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(V->getOperand(1)))
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if (CheckAndMask(V.getOperand(0), C, Val))
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return false;
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return true;
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}
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/// CheckOrImmediate - Check to see if the specified node is an or with an
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/// immediate returning true on failure.
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///
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/// FIXME: Inline this gunk into CheckOrMask.
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bool CheckOrImmediate(SDValue V, int64_t Val) {
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if (V->getOpcode() == ISD::OR)
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(V->getOperand(1)))
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if (CheckOrMask(V.getOperand(0), C, Val))
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return false;
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return true;
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}
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static int8_t GetInt1(const unsigned char *MatcherTable, unsigned &Idx) {
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return MatcherTable[Idx++];
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}
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static int16_t GetInt2(const unsigned char *MatcherTable, unsigned &Idx) {
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int16_t Val = GetInt1(MatcherTable, Idx);
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Val |= int16_t(GetInt1(MatcherTable, Idx)) << 8;
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return Val;
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}
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static int32_t GetInt4(const unsigned char *MatcherTable, unsigned &Idx) {
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int32_t Val = GetInt2(MatcherTable, Idx);
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Val |= int32_t(GetInt2(MatcherTable, Idx)) << 16;
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return Val;
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}
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static int64_t GetInt8(const unsigned char *MatcherTable, unsigned &Idx) {
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int64_t Val = GetInt4(MatcherTable, Idx);
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Val |= int64_t(GetInt4(MatcherTable, Idx)) << 32;
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return Val;
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}
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enum BuiltinOpcodes {
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OPC_Emit,
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OPC_Push,
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OPC_Record,
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|
|
OPC_MoveChild,
|
|
|
|
OPC_MoveParent,
|
|
|
|
OPC_CheckSame,
|
|
|
|
OPC_CheckPatternPredicate,
|
|
|
|
OPC_CheckPredicate,
|
|
|
|
OPC_CheckOpcode,
|
|
|
|
OPC_CheckType,
|
|
|
|
OPC_CheckInteger1, OPC_CheckInteger2, OPC_CheckInteger4, OPC_CheckInteger8,
|
|
|
|
OPC_CheckCondCode,
|
|
|
|
OPC_CheckValueType,
|
|
|
|
OPC_CheckComplexPat,
|
|
|
|
OPC_CheckAndImm1, OPC_CheckAndImm2, OPC_CheckAndImm4, OPC_CheckAndImm8,
|
|
|
|
OPC_CheckOrImm1, OPC_CheckOrImm2, OPC_CheckOrImm4, OPC_CheckOrImm8
|
|
|
|
};
|
|
|
|
|
|
|
|
struct MatchScope {
|
|
|
|
/// FailIndex - If this match fails, this is the index to continue with.
|
|
|
|
unsigned FailIndex;
|
|
|
|
|
|
|
|
/// NodeStackSize - The size of the node stack when the scope was formed.
|
|
|
|
unsigned NodeStackSize;
|
|
|
|
|
|
|
|
/// NumRecordedNodes - The number of recorded nodes when the scope was formed.
|
|
|
|
unsigned NumRecordedNodes;
|
|
|
|
};
|
|
|
|
|
|
|
|
SDNode *SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
|
|
|
|
unsigned TableSize) {
|
|
|
|
switch (NodeToMatch->getOpcode()) {
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
case ISD::EntryToken: // These nodes remain the same.
|
|
|
|
case ISD::BasicBlock:
|
|
|
|
case ISD::Register:
|
|
|
|
case ISD::HANDLENODE:
|
|
|
|
case ISD::TargetConstant:
|
|
|
|
case ISD::TargetConstantFP:
|
|
|
|
case ISD::TargetConstantPool:
|
|
|
|
case ISD::TargetFrameIndex:
|
|
|
|
case ISD::TargetExternalSymbol:
|
|
|
|
case ISD::TargetBlockAddress:
|
|
|
|
case ISD::TargetJumpTable:
|
|
|
|
case ISD::TargetGlobalTLSAddress:
|
|
|
|
case ISD::TargetGlobalAddress:
|
|
|
|
case ISD::TokenFactor:
|
|
|
|
case ISD::CopyFromReg:
|
|
|
|
case ISD::CopyToReg:
|
|
|
|
return 0;
|
|
|
|
case ISD::AssertSext:
|
|
|
|
case ISD::AssertZext:
|
|
|
|
ReplaceUses(SDValue(NodeToMatch, 0), NodeToMatch->getOperand(0));
|
|
|
|
return 0;
|
|
|
|
case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
|
|
|
|
case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch);
|
|
|
|
case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
|
|
|
|
|
|
|
|
SmallVector<MatchScope, 8> MatchScopes;
|
|
|
|
|
|
|
|
// RecordedNodes - This is the set of nodes that have been recorded by the
|
|
|
|
// state machine.
|
|
|
|
SmallVector<SDValue, 8> RecordedNodes;
|
|
|
|
|
|
|
|
// Set up the node stack with NodeToMatch as the only node on the stack.
|
|
|
|
SmallVector<SDValue, 8> NodeStack;
|
|
|
|
SDValue N = SDValue(NodeToMatch, 0);
|
|
|
|
NodeStack.push_back(N);
|
|
|
|
|
|
|
|
// Interpreter starts at opcode #0.
|
|
|
|
unsigned MatcherIndex = 0;
|
|
|
|
while (1) {
|
|
|
|
assert(MatcherIndex < TableSize && "Invalid index");
|
|
|
|
switch ((BuiltinOpcodes)MatcherTable[MatcherIndex++]) {
|
|
|
|
case OPC_Emit: {
|
|
|
|
errs() << "EMIT NODE\n";
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
case OPC_Push: {
|
|
|
|
unsigned NumToSkip = MatcherTable[MatcherIndex++];
|
|
|
|
MatchScope NewEntry;
|
|
|
|
NewEntry.FailIndex = MatcherIndex+NumToSkip;
|
|
|
|
NewEntry.NodeStackSize = NodeStack.size();
|
|
|
|
NewEntry.NumRecordedNodes = RecordedNodes.size();
|
|
|
|
MatchScopes.push_back(NewEntry);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
case OPC_Record:
|
|
|
|
// Remember this node, it may end up being an operand in the pattern.
|
|
|
|
RecordedNodes.push_back(N);
|
|
|
|
continue;
|
|
|
|
|
|
|
|
case OPC_MoveChild: {
|
|
|
|
unsigned Child = MatcherTable[MatcherIndex++];
|
|
|
|
if (Child >= N.getNumOperands())
|
|
|
|
break; // Match fails if out of range child #.
|
|
|
|
N = N.getOperand(Child);
|
|
|
|
NodeStack.push_back(N);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
case OPC_MoveParent:
|
|
|
|
// Pop the current node off the NodeStack.
|
|
|
|
NodeStack.pop_back();
|
|
|
|
assert(!NodeStack.empty() && "Node stack imbalance!");
|
|
|
|
N = NodeStack.back();
|
|
|
|
continue;
|
|
|
|
|
|
|
|
case OPC_CheckSame: {
|
|
|
|
// Accept if it is exactly the same as a previously recorded node.
|
|
|
|
unsigned RecNo = MatcherTable[MatcherIndex++];
|
|
|
|
assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
|
|
|
|
if (N != RecordedNodes[RecNo]) break;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
case OPC_CheckPatternPredicate: {
|
|
|
|
unsigned PredNo = MatcherTable[MatcherIndex++];
|
|
|
|
(void)PredNo;
|
|
|
|
// FIXME: CHECK IT.
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
case OPC_CheckPredicate: {
|
|
|
|
unsigned PredNo = MatcherTable[MatcherIndex++];
|
|
|
|
(void)PredNo;
|
|
|
|
// FIXME: CHECK IT.
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
case OPC_CheckComplexPat: {
|
|
|
|
unsigned PatNo = MatcherTable[MatcherIndex++];
|
|
|
|
(void)PatNo;
|
|
|
|
// FIXME: CHECK IT.
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
case OPC_CheckOpcode:
|
|
|
|
if (N->getOpcode() != MatcherTable[MatcherIndex++]) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckType:
|
|
|
|
if (N.getValueType() !=
|
|
|
|
(MVT::SimpleValueType)MatcherTable[MatcherIndex++]) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckCondCode:
|
|
|
|
if (cast<CondCodeSDNode>(N)->get() !=
|
|
|
|
(ISD::CondCode)MatcherTable[MatcherIndex++]) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckValueType:
|
|
|
|
if (cast<VTSDNode>(N)->getVT() !=
|
|
|
|
(MVT::SimpleValueType)MatcherTable[MatcherIndex++]) break;
|
|
|
|
continue;
|
|
|
|
|
|
|
|
case OPC_CheckInteger1:
|
|
|
|
if (CheckInteger(N, GetInt1(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckInteger2:
|
|
|
|
if (CheckInteger(N, GetInt2(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckInteger4:
|
|
|
|
if (CheckInteger(N, GetInt4(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckInteger8:
|
|
|
|
if (CheckInteger(N, GetInt8(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
|
|
|
|
case OPC_CheckAndImm1:
|
|
|
|
if (CheckAndImmediate(N, GetInt1(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckAndImm2:
|
|
|
|
if (CheckAndImmediate(N, GetInt2(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckAndImm4:
|
|
|
|
if (CheckAndImmediate(N, GetInt4(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckAndImm8:
|
|
|
|
if (CheckAndImmediate(N, GetInt8(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
|
|
|
|
case OPC_CheckOrImm1:
|
|
|
|
if (CheckOrImmediate(N, GetInt1(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckOrImm2:
|
|
|
|
if (CheckOrImmediate(N, GetInt2(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckOrImm4:
|
|
|
|
if (CheckOrImmediate(N, GetInt4(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
case OPC_CheckOrImm8:
|
|
|
|
if (CheckOrImmediate(N, GetInt8(MatcherTable, MatcherIndex))) break;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the code reached this point, then the match failed pop out to the next
|
|
|
|
// match scope.
|
|
|
|
if (MatchScopes.empty()) {
|
|
|
|
CannotYetSelect(NodeToMatch);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
RecordedNodes.resize(MatchScopes.back().NumRecordedNodes);
|
|
|
|
NodeStack.resize(MatchScopes.back().NodeStackSize);
|
|
|
|
MatcherIndex = MatchScopes.back().FailIndex;
|
|
|
|
MatchScopes.pop_back();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-05-14 10:17:11 +00:00
|
|
|
#endif /* LLVM_CODEGEN_DAGISEL_HEADER_H */
|