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llvm-6502/test/MC/Disassembler/neon-tests.txt

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Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
# CHECK: vbif q15, q7, q0
0x50 0xe1 0x7e 0xf3
# CHECK: vcvt.f32.s32 q15, q0, #1
0x50 0xee 0xff 0xf2
# CHECK: vdup.32 q3, d1[0]
0x41 0x6c 0xb4 0xf3
ARM disassembler did not react to recent changes to the NEON instruction table. VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 16:20:34 +00:00
# VLD1q8_UPD (with ${dst:dregpair} operand)
# CHECK: vld1.8 {d17, d18}, [r6], r5
0x05 0x1a 0x66 0xf4
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7
0x07 0x00 0x22 0xf4
# CHECK: vld4.8 {d4, d6, d8, d10}, [r2]
0x0f 0x41 0x22 0xf4
# CHECK: vmov d0, d15
0x1f 0x01 0x2f 0xf2
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:40:20 +00:00
# CHECK: vmov.i64 q6, #0xFF00FF00FF
Minor change to make the test case comply with Vd<0> == '0' when Q == '1'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:48:31 +00:00
0x75 0xce 0x81 0xf2
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:40:20 +00:00
Add support for disassembling VMVN (immediate) instructions. PR7747. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31 05:57:44 +00:00
# CHECK: vmvn.i32 d0, #0x0
0x30 0x00 0x80 0xf2
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
# CHECK: vmul.f32 d0, d0, d6
0x16 0x0d 0x00 0xf3
# CHECK: vneg.f32 q0, q0
0xc0 0x07 0xb9 0xf3
# CHECK: vqrdmulh.s32 d0, d0, d3[1]
0x63 0x0d 0xa0 0xf2
# CHECK: vrshr.s32 d0, d0, #16
0x10 0x02 0xb0 0xf2
# CHECK: vshll.i16 q3, d1, #16
0x01 0x63 0xb6 0xf3
# CHECK: vsri.32 q15, q0, #1
0x50 0xe4 0xff 0xf3
# CHECK: vtbx.8 d18, {d4, d5, d6}, d7
0x47 0x2a 0xf4 0xf3
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