llvm-6502/test/CodeGen/X86/vec_set-9.ll

; RUN: llc < %s -march=x86-64 | FileCheck %s

; CHECK: test3
; CHECK: movd
; CHECK-NOT: movd
; CHECK: {{movlhps.*%xmm0, %xmm0}}
; CHECK-NEXT: ret

define <2 x i64> @test3(i64 %A) nounwind {
entry:
	%B = insertelement <2 x i64> undef, i64 %A, i32 1
	ret <2 x i64> %B
}
Rewrite X86 codegen regression test with FileCheck git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180776 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 07:51:08 +00:00			`; RUN: llc < %s -march=x86-64 \| FileCheck %s`

			`; CHECK: test3`
			`; CHECK: movd`
			`; CHECK-NOT: movd`
			`; CHECK: {{movlhps.*%xmm0, %xmm0}}`
			`; CHECK-NEXT: ret`
Teach SD some vector identities, allowing us to compile vec_set-9 into: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48058 91177308-0d34-0410-b5e6-96231b3b80d8 2008-03-08 23:43:36 +00:00
Add nounwind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50837 91177308-0d34-0410-b5e6-96231b3b80d8 2008-05-07 22:59:08 +00:00			`define <2 x i64> @test3(i64 %A) nounwind {`
Teach SD some vector identities, allowing us to compile vec_set-9 into: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48058 91177308-0d34-0410-b5e6-96231b3b80d8 2008-03-08 23:43:36 +00:00			`entry:`
			`%B = insertelement <2 x i64> undef, i64 %A, i32 1`
			`ret <2 x i64> %B`
			`}`