2014-03-31 12:13:12 +00:00
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# Instructions that are valid
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#
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2014-04-10 13:16:49 +00:00
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# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
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2014-03-31 12:13:12 +00:00
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.set noat
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abs.d $f7,$f25 # CHECK: encoding
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abs.s $f9,$f16
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add $s7,$s2,$a1
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add.d $f1,$f7,$f29
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add.s $f8,$f21,$f24
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addi $t5,$t1,26322
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addu $t1,$a0,$a2
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and $s7,$v0,$t4
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c.ngl.d $f29,$f29
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c.ngle.d $f0,$f16
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c.sf.d $f30,$f0
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c.sf.s $f14,$f22
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ceil.l.d $f1,$f3
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ceil.l.s $f18,$f13
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ceil.w.d $f11,$f25
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ceil.w.s $f6,$f20
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cfc1 $s1,$21
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ctc1 $a2,$26
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cvt.d.l $f4,$f16
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cvt.d.s $f22,$f28
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cvt.d.w $f26,$f11
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cvt.l.d $f24,$f15
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cvt.l.s $f11,$f29
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cvt.s.d $f26,$f8
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cvt.s.l $f15,$f30
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cvt.s.w $f22,$f15
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cvt.w.d $f20,$f14
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cvt.w.s $f20,$f24
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dadd $s3,$at,$ra
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daddi $sp,$s4,-27705
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daddiu $k0,$s6,-4586
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[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:35:28 +00:00
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ddiv $zero,$k0,$s3
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ddivu $zero,$s0,$s1
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div $zero,$t9,$t3
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2014-03-31 12:13:12 +00:00
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div.d $f29,$f20,$f27
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div.s $f4,$f5,$f15
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[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:35:28 +00:00
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divu $zero,$t9,$t7
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2014-03-31 12:13:12 +00:00
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dmfc1 $t4,$f13
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dmtc1 $s0,$f14
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dmult $s7,$t1
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dmultu $a1,$a2
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dsllv $zero,$s4,$t4
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dsrav $gp,$s2,$s3
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dsrlv $s3,$t6,$s4
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dsub $a3,$s6,$t0
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dsubu $a1,$a1,$k0
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2014-04-03 13:21:51 +00:00
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ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
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2014-03-31 12:13:12 +00:00
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eret
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floor.l.d $f26,$f7
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floor.l.s $f12,$f5
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floor.w.d $f14,$f11
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floor.w.s $f8,$f9
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lb $t8,-14515($t2)
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lbu $t0,30195($v1)
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ld $sp,-28645($s1)
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ldc1 $f11,16391($s0)
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ldc2 $8,-21181($at)
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ldl $t8,-4167($t8)
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ldr $t6,-30358($s4)
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ldxc1 $f8,$s7($t7)
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lh $t3,-8556($s5)
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lhu $s3,-22851($v0)
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li $at,-29773
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li $zero,-29889
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ll $v0,-7321($s2)
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lld $zero,-14736($ra)
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lw $t0,5674($a1)
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lwc1 $f16,10225($k0)
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lwc2 $18,-841($a2)
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lwl $s4,-4231($t7)
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lwr $zero,-19147($gp)
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lwu $s3,-24086($v1)
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lwxc1 $f12,$s1($s8)
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mfc1 $a3,$f27
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mfhi $s3
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mfhi $sp
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mflo $s1
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mov.d $f20,$f14
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mov.s $f2,$f27
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move $a0,$a3
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move $s5,$a0
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move $s8,$a0
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move $t9,$a2
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movf $gp,$t0,$fcc7
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movf.d $f6,$f11,$fcc5
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movf.s $f23,$f5,$fcc6
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movn $v1,$s1,$s0
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movn.d $f27,$f21,$k0
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movn.s $f12,$f0,$s7
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movt $zero,$s4,$fcc5
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movt.d $f0,$f2,$fcc0
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movt.s $f30,$f2,$fcc1
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movz $a1,$s6,$t1
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movz.d $f12,$f29,$t1
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movz.s $f25,$f7,$v1
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mtc1 $s8,$f9
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mthi $s1
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mtlo $sp
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mtlo $t9
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mul.d $f20,$f20,$f16
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mul.s $f30,$f10,$f2
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mult $sp,$s4
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mult $sp,$v0
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multu $gp,$k0
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multu $t1,$s2
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neg.d $f27,$f18
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neg.s $f1,$f15
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nop
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nor $a3,$zero,$a3
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or $t4,$s0,$sp
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round.l.d $f12,$f1
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round.l.s $f25,$f5
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round.w.d $f6,$f4
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round.w.s $f27,$f28
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sb $s6,-19857($t6)
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sc $t7,18904($s3)
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scd $t7,-8243($sp)
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sd $t4,5835($t2)
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sdc1 $f31,30574($t5)
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sdc2 $20,23157($s2)
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sdl $a3,-20961($s8)
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sdr $t3,-20423($t4)
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sdxc1 $f11,$t2($t6)
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sh $t6,-6704($t7)
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sllv $a3,$zero,$t1
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slt $s7,$t3,$k1
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slti $s1,$t2,9489
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sltiu $t9,$t9,-15531
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sltu $s4,$s5,$t3
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sqrt.d $f17,$f22
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sqrt.s $f0,$f1
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srav $s1,$s7,$sp
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srlv $t9,$s4,$a0
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2014-04-03 13:21:51 +00:00
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ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
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2014-03-31 12:13:12 +00:00
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sub $s6,$s3,$t4
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sub.d $f18,$f3,$f17
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sub.s $f23,$f22,$f22
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subu $sp,$s6,$s6
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sw $ra,-10160($sp)
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swc1 $f6,-8465($t8)
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swc2 $25,24880($s0)
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swl $t7,13694($s3)
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swr $s1,-26590($t6)
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swxc1 $f19,$t4($k0)
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teqi $s5,-17504
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tgei $s1,5025
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tgeiu $sp,-28621
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tlti $t6,-21059
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tltiu $ra,-5076
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tnei $t4,-29647
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trunc.l.d $f23,$f23
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trunc.l.s $f28,$f31
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trunc.w.d $f22,$f15
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trunc.w.s $f28,$f30
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xor $s2,$a0,$s8
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