[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; Verify that each of the following test cases is folded into a single
|
|
|
|
|
; instruction which performs a blend operation.
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test1:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
|
|
|
|
|
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
|
|
|
|
|
%or = or <2 x i64> %shuf1, %shuf2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test2:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test3:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
|
|
|
|
|
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
|
|
|
|
|
%or = or <2 x i64> %shuf1, %shuf2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test4:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test5:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test6:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test7:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0>
|
|
|
|
|
%and2 = and <4 x i32> %b, <i32 0, i32 0, i32 -1, i32 -1>
|
|
|
|
|
%or = or <4 x i32> %and1, %and2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test8:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%and1 = and <2 x i64> %a, <i64 -1, i64 0>
|
|
|
|
|
%and2 = and <2 x i64> %b, <i64 0, i64 -1>
|
|
|
|
|
%or = or <2 x i64> %and1, %and2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test9:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1>
|
|
|
|
|
%and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0>
|
|
|
|
|
%or = or <4 x i32> %and1, %and2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test10:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%and1 = and <2 x i64> %a, <i64 0, i64 -1>
|
|
|
|
|
%and2 = and <2 x i64> %b, <i64 -1, i64 0>
|
|
|
|
|
%or = or <2 x i64> %and1, %and2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test11:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0>
|
|
|
|
|
%and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%or = or <4 x i32> %and1, %and2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test12:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%and1 = and <4 x i32> %a, <i32 0, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%and2 = and <4 x i32> %b, <i32 -1, i32 0, i32 0, i32 0>
|
|
|
|
|
%or = or <4 x i32> %and1, %and2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; Verify that the following test cases are folded into single shuffles.
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test13:
|
|
|
|
|
; CHECK: # BB#0:
|
2015-02-16 01:52:02 +00:00
|
|
|
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
|
|
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test14:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
|
|
|
|
|
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
|
|
|
|
|
%or = or <2 x i64> %shuf1, %shuf2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test15:
|
|
|
|
|
; CHECK: # BB#0:
|
2015-02-16 01:52:02 +00:00
|
|
|
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,2,1]
|
|
|
|
|
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,2,3]
|
|
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test16:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
|
|
|
; CHECK-NEXT: movdqa %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
|
|
|
|
|
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
|
|
|
|
|
%or = or <2 x i64> %shuf1, %shuf2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; Verify that the dag-combiner does not fold a OR of two shuffles into a single
|
|
|
|
|
; shuffle instruction when the shuffle indexes are not compatible.
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
|
2015-02-03 21:58:29 +00:00
|
|
|
; CHECK-LABEL: test17:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: psllq $32, %xmm0
|
|
|
|
|
; CHECK-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
|
|
|
|
|
; CHECK-NEXT: por %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test18:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-12-02 22:31:23 +00:00
|
|
|
; CHECK-NEXT: pxor %xmm2, %xmm2
|
|
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
|
2014-12-02 22:31:23 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: por %xmm1, %xmm0
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test19:
|
|
|
|
|
; CHECK: # BB#0:
|
2015-02-16 01:52:02 +00:00
|
|
|
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3]
|
|
|
|
|
; CHECK-NEXT: pxor %xmm3, %xmm3
|
|
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
|
|
|
|
|
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
|
|
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7]
|
|
|
|
|
; CHECK-NEXT: por %xmm2, %xmm0
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
|
|
|
|
|
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
|
|
|
|
|
%or = or <4 x i32> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i32> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test20:
|
|
|
|
|
; CHECK: # BB#0:
|
2015-02-16 21:50:56 +00:00
|
|
|
; CHECK-NEXT: por %xmm1, %xmm0
|
2015-02-15 09:26:15 +00:00
|
|
|
; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
|
|
|
|
|
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
|
|
|
|
|
%or = or <2 x i64> %shuf1, %shuf2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test21:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-25 22:34:59 +00:00
|
|
|
; CHECK-NEXT: por %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
|
|
|
|
|
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
|
|
|
|
|
%or = or <2 x i64> %shuf1, %shuf2
|
|
|
|
|
ret <2 x i64> %or
|
|
|
|
|
}
|
|
|
|
|
|
2015-04-23 08:43:13 +00:00
|
|
|
|
|
|
|
|
; Verify that the dag-combiner keeps the correct domain for float/double vectors
|
|
|
|
|
; bitcast to use the mask-or blend combine.
|
|
|
|
|
|
|
|
|
|
define <2 x double> @test22(<2 x double> %a0, <2 x double> %a1) {
|
|
|
|
|
; CHECK-LABEL: test22:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%bc1 = bitcast <2 x double> %a0 to <2 x i64>
|
|
|
|
|
%bc2 = bitcast <2 x double> %a1 to <2 x i64>
|
|
|
|
|
%and1 = and <2 x i64> %bc1, <i64 0, i64 -1>
|
|
|
|
|
%and2 = and <2 x i64> %bc2, <i64 -1, i64 0>
|
|
|
|
|
%or = or <2 x i64> %and1, %and2
|
|
|
|
|
%bc3 = bitcast <2 x i64> %or to <2 x double>
|
|
|
|
|
ret <2 x double> %bc3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x float> @test23(<4 x float> %a0, <4 x float> %a1) {
|
|
|
|
|
; CHECK-LABEL: test23:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%bc1 = bitcast <4 x float> %a0 to <4 x i32>
|
|
|
|
|
%bc2 = bitcast <4 x float> %a1 to <4 x i32>
|
|
|
|
|
%and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0>
|
|
|
|
|
%and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1>
|
|
|
|
|
%or = or <4 x i32> %and1, %and2
|
|
|
|
|
%bc3 = bitcast <4 x i32> %or to <4 x float>
|
|
|
|
|
ret <4 x float> %bc3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x float> @test24(<4 x float> %a0, <4 x float> %a1) {
|
|
|
|
|
; CHECK-LABEL: test24:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%bc1 = bitcast <4 x float> %a0 to <2 x i64>
|
|
|
|
|
%bc2 = bitcast <4 x float> %a1 to <2 x i64>
|
|
|
|
|
%and1 = and <2 x i64> %bc1, <i64 0, i64 -1>
|
|
|
|
|
%and2 = and <2 x i64> %bc2, <i64 -1, i64 0>
|
|
|
|
|
%or = or <2 x i64> %and1, %and2
|
|
|
|
|
%bc3 = bitcast <2 x i64> %or to <4 x float>
|
|
|
|
|
ret <4 x float> %bc3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define <4 x float> @test25(<4 x float> %a0) {
|
|
|
|
|
; CHECK-LABEL: test25:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3]
|
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
|
%bc1 = bitcast <4 x float> %a0 to <4 x i32>
|
|
|
|
|
%bc2 = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32>
|
|
|
|
|
%and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0>
|
|
|
|
|
%and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1>
|
|
|
|
|
%or = or <4 x i32> %and1, %and2
|
|
|
|
|
%bc3 = bitcast <4 x i32> %or to <4 x float>
|
|
|
|
|
ret <4 x float> %bc3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2014-07-15 00:02:32 +00:00
|
|
|
; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle
|
|
|
|
|
; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to
|
|
|
|
|
; handle legal vector value types.
|
|
|
|
|
define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) {
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-LABEL: test_crash:
|
|
|
|
|
; CHECK: # BB#0:
|
2014-11-04 23:25:08 +00:00
|
|
|
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
2014-10-03 01:06:32 +00:00
|
|
|
; CHECK-NEXT: retq
|
2014-07-15 00:02:32 +00:00
|
|
|
%shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
|
|
|
|
|
%shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
|
|
|
|
|
%or = or <4 x i8> %shuf1, %shuf2
|
|
|
|
|
ret <4 x i8> %or
|
|
|
|
|
}
|
[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two
shufflevector into a single shuffle vector when possible.
The rules are:
1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
The DAGCombiner can take advantage of the fact that OR is commutative and
compute two possible shuffle masks (Mask1 and Mask2) for the resulting
shuffle node.
Before folding a dag according to either rule 1 or 2, DAGCombiner verifies
that the resulting shuffle mask is legal for the target.
DAGCombiner would firstly try to fold according to 1.; If not possible
then it will try to fold according to 2.
If both Mask1 and Mask2 are illegal then we conservatively don't fold
the OR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:19:52 +00:00
|
|
|
|
