2005-01-07 07:46:03 +00:00
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//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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2005-04-21 20:39:54 +00:00
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//
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2005-01-07 07:46:03 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 19:59:42 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 20:39:54 +00:00
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//
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2005-01-07 07:46:03 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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2013-01-10 00:45:19 +00:00
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#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
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#define LLVM_CODEGEN_SELECTIONDAGISEL_H
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2005-01-07 07:46:03 +00:00
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2009-07-31 18:16:33 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2012-12-03 17:02:12 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/BasicBlock.h"
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2012-12-03 17:02:12 +00:00
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#include "llvm/Pass.h"
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2005-01-07 07:46:03 +00:00
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namespace llvm {
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2008-09-03 23:12:08 +00:00
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class FastISel;
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2009-11-23 18:04:58 +00:00
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class SelectionDAGBuilder;
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2008-07-27 21:46:04 +00:00
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class SDValue;
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2007-12-31 04:13:23 +00:00
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class MachineRegisterInfo;
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2005-01-07 07:46:03 +00:00
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class TargetLowering;
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2011-12-08 22:15:21 +00:00
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class TargetLibraryInfo;
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2005-01-07 07:46:03 +00:00
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class FunctionLoweringInfo;
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2009-01-15 22:18:12 +00:00
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class ScheduleHazardRecognizer;
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2008-08-17 18:44:35 +00:00
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class GCFunctionInfo;
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2009-02-11 04:27:20 +00:00
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class ScheduleDAGSDNodes;
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implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 02:18:34 +00:00
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class LoadInst;
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2010-12-24 04:28:06 +00:00
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2005-01-07 07:46:03 +00:00
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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2009-07-31 18:16:33 +00:00
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class SelectionDAGISel : public MachineFunctionPass {
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2005-01-07 07:46:03 +00:00
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public:
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2013-06-19 21:36:55 +00:00
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TargetMachine &TM;
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2011-12-08 22:15:21 +00:00
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const TargetLibraryInfo *LibInfo;
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2008-08-27 23:52:12 +00:00
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FunctionLoweringInfo *FuncInfo;
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2009-01-15 19:20:50 +00:00
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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2005-01-07 07:46:03 +00:00
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SelectionDAG *CurDAG;
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2009-11-23 18:04:58 +00:00
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SelectionDAGBuilder *SDB;
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2007-08-27 16:26:13 +00:00
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AliasAnalysis *AA;
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2008-08-17 18:44:35 +00:00
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GCFunctionInfo *GFI;
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2009-04-29 23:29:43 +00:00
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CodeGenOpt::Level OptLevel;
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2007-05-03 01:11:54 +00:00
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static char ID;
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2005-01-07 07:46:03 +00:00
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2013-06-19 21:36:55 +00:00
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explicit SelectionDAGISel(TargetMachine &tm,
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2009-04-29 23:29:43 +00:00
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CodeGenOpt::Level OL = CodeGenOpt::Default);
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2008-08-27 23:52:12 +00:00
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virtual ~SelectionDAGISel();
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2010-12-24 04:28:06 +00:00
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2013-06-19 21:36:55 +00:00
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const TargetLowering *getTargetLowering() const {
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return TM.getTargetLowering();
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}
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2005-01-07 07:46:03 +00:00
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2005-08-17 06:46:50 +00:00
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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2005-01-07 07:46:03 +00:00
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2009-07-31 18:16:33 +00:00
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virtual bool runOnMachineFunction(MachineFunction &MF);
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2005-01-07 07:46:03 +00:00
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2010-04-14 20:17:22 +00:00
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virtual void EmitFunctionEntryCode() {}
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2010-12-24 04:28:06 +00:00
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2010-03-02 06:34:30 +00:00
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/// PreprocessISelDAG - This hook allows targets to hack on the graph before
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/// instruction selection starts.
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virtual void PreprocessISelDAG() {}
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2010-12-24 04:28:06 +00:00
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2010-03-02 06:34:30 +00:00
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/// PostprocessISelDAG() - This hook allows the target to hack on the graph
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/// right after selection.
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virtual void PostprocessISelDAG() {}
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2010-12-24 04:28:06 +00:00
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2010-03-02 06:34:30 +00:00
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/// Select - Main hook targets implement to select a node.
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virtual SDNode *Select(SDNode *N) = 0;
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2010-12-24 04:28:06 +00:00
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2006-02-24 02:12:52 +00:00
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/// SelectInlineAsmMemoryOperand - Select the specified address as a target
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/// addressing mode, according to the specified constraint code. If this does
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/// not match or is not implemented, return true. The resultant operands
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/// (which will appear in the machine instruction) should be added to the
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/// OutOps vector.
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2008-07-27 21:46:04 +00:00
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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2006-02-24 02:12:52 +00:00
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char ConstraintCode,
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2008-08-23 02:25:05 +00:00
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std::vector<SDValue> &OutOps) {
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2006-02-24 02:12:52 +00:00
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return true;
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}
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2006-07-27 06:36:49 +00:00
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2010-02-15 19:41:07 +00:00
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/// IsProfitableToFold - Returns true if it's profitable to fold the specific
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/// operand node N of U during instruction selection that starts at Root.
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virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
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/// IsLegalToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root.
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2011-10-24 23:48:32 +00:00
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/// FIXME: This is a static member function because the MSP430/X86
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2010-10-11 05:48:00 +00:00
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/// targets, which uses it during isel. This could become a proper member.
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2010-04-17 15:26:15 +00:00
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static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
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CodeGenOpt::Level OptLevel,
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bool IgnoreChains = false);
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2009-05-08 18:51:58 +00:00
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2010-02-28 21:58:42 +00:00
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// Opcodes used by the DAG state machine:
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enum BuiltinOpcodes {
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OPC_Scope,
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OPC_RecordNode,
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2010-12-24 04:28:06 +00:00
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OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
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2010-02-28 21:58:42 +00:00
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OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
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OPC_RecordMemRef,
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2010-12-23 17:24:32 +00:00
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OPC_CaptureGlueInput,
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2010-02-28 21:58:42 +00:00
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OPC_MoveChild,
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OPC_MoveParent,
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OPC_CheckSame,
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2013-10-05 05:38:16 +00:00
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OPC_CheckChild0Same, OPC_CheckChild1Same,
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OPC_CheckChild2Same, OPC_CheckChild3Same,
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2010-02-28 21:58:42 +00:00
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OPC_CheckPatternPredicate,
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OPC_CheckPredicate,
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OPC_CheckOpcode,
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2010-03-01 06:59:22 +00:00
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OPC_SwitchOpcode,
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2010-02-28 21:58:42 +00:00
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OPC_CheckType,
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2010-03-03 06:28:15 +00:00
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OPC_SwitchType,
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2010-02-28 21:58:42 +00:00
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OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
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OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
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OPC_CheckChild6Type, OPC_CheckChild7Type,
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2010-02-28 22:14:32 +00:00
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OPC_CheckInteger,
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2014-02-05 05:44:28 +00:00
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OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
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OPC_CheckChild3Integer, OPC_CheckChild4Integer,
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2010-02-28 21:58:42 +00:00
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OPC_CheckCondCode,
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OPC_CheckValueType,
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OPC_CheckComplexPat,
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2010-02-28 22:14:32 +00:00
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OPC_CheckAndImm, OPC_CheckOrImm,
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2010-02-28 21:58:42 +00:00
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OPC_CheckFoldableChainNode,
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2010-12-24 04:28:06 +00:00
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2010-02-28 22:14:32 +00:00
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OPC_EmitInteger,
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2010-02-28 21:58:42 +00:00
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OPC_EmitRegister,
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2011-03-01 01:37:19 +00:00
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OPC_EmitRegister2,
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2010-02-28 21:58:42 +00:00
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OPC_EmitConvertToTarget,
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OPC_EmitMergeInputChains,
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2010-03-28 05:50:16 +00:00
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OPC_EmitMergeInputChains1_0,
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OPC_EmitMergeInputChains1_1,
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2010-02-28 21:58:42 +00:00
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OPC_EmitCopyToReg,
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OPC_EmitNodeXForm,
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OPC_EmitNode,
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OPC_MorphNodeTo,
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2010-12-23 17:24:32 +00:00
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OPC_MarkGlueResults,
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2010-02-28 21:58:42 +00:00
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OPC_CompleteMatch
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};
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2010-12-24 04:28:06 +00:00
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2010-02-28 21:58:42 +00:00
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enum {
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2010-12-23 17:24:32 +00:00
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OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
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2010-02-28 21:58:42 +00:00
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OPFL_Chain = 1, // Node has a chain input.
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2010-12-23 17:13:18 +00:00
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OPFL_GlueInput = 2, // Node has a glue input.
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OPFL_GlueOutput = 4, // Node has a glue output.
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2010-02-28 21:58:42 +00:00
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OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
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OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
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OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
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OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
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OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
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OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
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OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
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OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
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2010-12-24 04:28:06 +00:00
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2010-02-28 21:58:42 +00:00
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OPFL_VariadicInfo = OPFL_Variadic6
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};
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2010-12-24 04:28:06 +00:00
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2010-02-28 22:37:22 +00:00
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/// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
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/// number of fixed arity values that should be skipped when copying from the
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/// root.
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static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
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return ((Flags&OPFL_VariadicInfo) >> 4)-1;
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}
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2010-12-24 04:28:06 +00:00
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2005-08-18 18:44:33 +00:00
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protected:
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2008-07-01 18:49:06 +00:00
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/// DAGSize - Size of DAG being instruction selected.
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///
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unsigned DAGSize;
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2010-12-24 04:28:06 +00:00
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2010-03-02 06:04:12 +00:00
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/// ReplaceUses - replace all uses of the old node F with the use
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/// of the new node T.
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void ReplaceUses(SDValue F, SDValue T) {
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2012-04-20 22:08:46 +00:00
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CurDAG->ReplaceAllUsesOfValueWith(F, T);
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2010-03-02 06:04:12 +00:00
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}
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2010-12-24 04:28:06 +00:00
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2010-03-02 06:04:12 +00:00
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/// ReplaceUses - replace all uses of the old nodes F with the use
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/// of the new nodes T.
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void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
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2012-04-20 22:08:46 +00:00
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CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
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2010-03-02 06:04:12 +00:00
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}
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2010-12-24 04:28:06 +00:00
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2010-03-02 06:04:12 +00:00
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/// ReplaceUses - replace all uses of the old node F with the use
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/// of the new node T.
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void ReplaceUses(SDNode *F, SDNode *T) {
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2012-04-20 22:08:46 +00:00
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CurDAG->ReplaceAllUsesWith(F, T);
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2010-03-02 06:04:12 +00:00
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}
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2010-12-24 04:28:06 +00:00
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2008-07-01 18:49:06 +00:00
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2006-02-24 02:12:52 +00:00
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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2008-08-23 02:25:05 +00:00
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void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
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2006-07-27 06:36:49 +00:00
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2010-12-24 04:28:06 +00:00
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2010-03-03 07:31:15 +00:00
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public:
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2006-10-11 03:58:02 +00:00
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// Calls to these predicates are generated by tblgen.
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2008-07-27 21:46:04 +00:00
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bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
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2007-07-24 23:00:27 +00:00
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int64_t DesiredMaskS) const;
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2008-07-27 21:46:04 +00:00
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bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
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2007-07-24 23:00:27 +00:00
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int64_t DesiredMaskS) const;
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2010-12-24 04:28:06 +00:00
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2010-02-16 07:21:10 +00:00
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/// CheckPatternPredicate - This function is generated by tblgen in the
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/// target. It runs the specified pattern predicate and returns true if it
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/// succeeds or false if it fails. The number is a private implementation
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/// detail to the code tblgen produces.
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virtual bool CheckPatternPredicate(unsigned PredNo) const {
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2012-02-05 22:14:15 +00:00
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llvm_unreachable("Tblgen should generate the implementation of this!");
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2010-02-16 07:21:10 +00:00
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}
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2010-02-22 04:10:52 +00:00
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/// CheckNodePredicate - This function is generated by tblgen in the target.
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/// It runs node predicate number PredNo and returns true if it succeeds or
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2010-02-16 07:21:10 +00:00
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/// false if it fails. The number is a private implementation
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/// detail to the code tblgen produces.
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virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
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2012-02-05 22:14:15 +00:00
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llvm_unreachable("Tblgen should generate the implementation of this!");
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2010-02-16 07:21:10 +00:00
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}
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2010-12-24 04:28:06 +00:00
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2010-09-21 20:37:12 +00:00
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virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
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unsigned PatternNo,
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2010-09-21 22:00:25 +00:00
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SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
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2012-02-05 22:14:15 +00:00
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llvm_unreachable("Tblgen should generate the implementation of this!");
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2010-02-17 00:41:34 +00:00
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}
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2010-12-24 04:28:06 +00:00
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2010-02-21 03:15:11 +00:00
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virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
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2012-02-05 22:14:15 +00:00
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llvm_unreachable("Tblgen should generate this!");
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2010-02-21 03:15:11 +00:00
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}
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2010-03-03 07:31:15 +00:00
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SDNode *SelectCodeCommon(SDNode *NodeToMatch,
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|
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const unsigned char *MatcherTable,
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|
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unsigned TableSize);
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2010-12-24 04:28:06 +00:00
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2010-03-03 07:31:15 +00:00
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private:
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2010-12-24 04:28:06 +00:00
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2009-10-29 22:30:23 +00:00
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// Calls to these functions are generated by tblgen.
|
2010-01-05 01:24:18 +00:00
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SDNode *Select_INLINEASM(SDNode *N);
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SDNode *Select_UNDEF(SDNode *N);
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void CannotYetSelect(SDNode *N);
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2009-10-29 22:30:23 +00:00
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2005-01-17 17:14:43 +00:00
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private:
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2010-03-02 06:34:30 +00:00
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void DoInstructionSelection();
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2010-03-02 06:55:04 +00:00
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SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
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const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
|
2010-12-24 04:28:06 +00:00
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|
2010-07-10 09:00:22 +00:00
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void PrepareEHLandingPad();
|
2013-02-28 23:09:18 +00:00
|
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|
|
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/// \brief Perform instruction selection on all basic blocks in the function.
|
2010-04-15 01:51:59 +00:00
|
|
|
void SelectAllBasicBlocks(const Function &Fn);
|
2005-04-21 20:39:54 +00:00
|
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|
|
2013-02-28 23:09:18 +00:00
|
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|
/// \brief Perform instruction selection on a single basic block, for
|
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/// instructions between \p Begin and \p End. \p HadTailCall will be set
|
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|
|
/// to true if a call in the block was translated as a tail call.
|
2010-10-25 21:31:46 +00:00
|
|
|
void SelectBasicBlock(BasicBlock::const_iterator Begin,
|
2010-07-10 09:00:22 +00:00
|
|
|
BasicBlock::const_iterator End,
|
|
|
|
bool &HadTailCall);
|
2013-02-28 23:09:18 +00:00
|
|
|
void FinishBasicBlock();
|
|
|
|
|
2010-07-10 09:00:22 +00:00
|
|
|
void CodeGenAndEmitDAG();
|
2013-02-28 23:09:18 +00:00
|
|
|
|
|
|
|
/// \brief Generate instructions for lowering the incoming arguments of the
|
|
|
|
/// given function.
|
|
|
|
void LowerArguments(const Function &F);
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
void ComputeLiveOutVRegInfo();
|
|
|
|
|
2009-02-06 18:26:51 +00:00
|
|
|
/// Create the scheduler. If a specific scheduler was specified
|
|
|
|
/// via the SchedulerRegistry, use it, otherwise select the
|
|
|
|
/// one preferred by the target.
|
|
|
|
///
|
2009-02-11 04:27:20 +00:00
|
|
|
ScheduleDAGSDNodes *CreateScheduler();
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2010-03-01 18:47:11 +00:00
|
|
|
/// OpcodeOffset - This is a cache used to dispatch efficiently into isel
|
|
|
|
/// state machines that start with a OPC_SwitchOpcode node.
|
|
|
|
std::vector<unsigned> OpcodeOffset;
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2010-12-23 17:13:18 +00:00
|
|
|
void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
|
|
|
|
const SmallVectorImpl<SDNode*> &ChainNodesMatched,
|
|
|
|
SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
|
|
|
|
bool isMorphNodeTo);
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2005-01-07 07:46:03 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2013-01-10 00:45:19 +00:00
|
|
|
#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
|