2008-01-01 01:12:31 +00:00
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//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
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2007-12-31 04:13:23 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2010-04-26 19:16:00 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2010-04-14 16:51:49 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2010-04-26 19:16:00 +00:00
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#include "llvm/Support/CommandLine.h"
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2007-12-31 04:13:23 +00:00
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using namespace llvm;
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2008-02-10 18:45:23 +00:00
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MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
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2007-12-31 04:13:23 +00:00
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VRegInfo.reserve(256);
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2009-06-14 20:22:55 +00:00
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RegAllocHints.reserve(256);
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2008-10-20 20:03:28 +00:00
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RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
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2008-02-10 18:45:23 +00:00
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UsedPhysRegs.resize(TRI.getNumRegs());
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2008-01-01 01:12:31 +00:00
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// Create the physreg use/def lists.
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2008-02-10 18:45:23 +00:00
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PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
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memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
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2008-01-01 01:12:31 +00:00
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}
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MachineRegisterInfo::~MachineRegisterInfo() {
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
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assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
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2008-07-07 19:55:35 +00:00
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for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
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assert(!PhysRegUseDefLists[i] &&
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"PhysRegUseDefLists has entries after all instructions are deleted");
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2008-01-01 01:12:31 +00:00
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#endif
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delete [] PhysRegUseDefLists;
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}
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2009-04-15 01:19:35 +00:00
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void
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MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
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unsigned VR = Reg;
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
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VRegInfo[Reg].first = RC;
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// Remove from old register class's vregs list. This may be slow but
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// fortunately this operation is rarely needed.
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std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
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std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
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VRegs.erase(I);
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// Add to new register class's vregs list.
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RegClass2VRegMap[RC->getID()].push_back(VR);
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}
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2008-12-08 04:54:11 +00:00
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned
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MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
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assert(RegClass && "Cannot create register without RegClass!");
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// Add a reg, but keep track of whether the vector reallocated or not.
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void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
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VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
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2009-06-15 08:28:29 +00:00
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RegAllocHints.push_back(std::make_pair(0, 0));
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2008-12-08 04:54:11 +00:00
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if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
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// The vector reallocated, handle this now.
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HandleVRegListReallocation();
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unsigned VR = getLastVirtReg();
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RegClass2VRegMap[RegClass->getID()].push_back(VR);
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return VR;
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}
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2008-01-01 01:12:31 +00:00
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/// HandleVRegListReallocation - We just added a virtual register to the
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/// VRegInfo info list and it reallocated. Update the use/def lists info
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/// pointers.
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void MachineRegisterInfo::HandleVRegListReallocation() {
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// The back pointers for the vreg lists point into the previous vector.
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// Update them to point to their correct slots.
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for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
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MachineOperand *List = VRegInfo[i].second;
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if (!List) continue;
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// Update the back-pointer to be accurate once more.
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List->Contents.Reg.Prev = &VRegInfo[i].second;
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}
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2007-12-31 04:13:23 +00:00
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}
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2008-01-01 03:07:29 +00:00
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2008-01-01 20:36:19 +00:00
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
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assert(FromReg != ToReg && "Cannot replace a reg with itself");
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// TODO: This could be more efficient by bulk changing the operands.
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for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
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MachineOperand &O = I.getOperand();
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++I;
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O.setReg(ToReg);
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}
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}
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2008-01-01 03:07:29 +00:00
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
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2008-02-10 18:45:23 +00:00
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assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
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2008-01-01 03:07:29 +00:00
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"Invalid vreg!");
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2009-09-25 22:26:13 +00:00
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// Since we are in SSA form, we can use the first definition.
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if (!def_empty(Reg))
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return &*def_begin(Reg);
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2008-01-01 03:07:29 +00:00
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return 0;
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}
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2008-02-13 02:45:38 +00:00
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2010-03-03 21:18:38 +00:00
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bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
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use_iterator UI = use_begin(RegNo);
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if (UI == use_end())
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return false;
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return ++UI == use_end();
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}
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bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
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use_nodbg_iterator UI = use_nodbg_begin(RegNo);
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if (UI == use_nodbg_end())
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return false;
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return ++UI == use_nodbg_end();
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}
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2008-02-13 02:45:38 +00:00
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2010-04-13 16:55:37 +00:00
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bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == Reg || I->second == Reg)
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return true;
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return false;
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}
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bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
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for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
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if (*I == Reg)
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return true;
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return false;
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}
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2010-04-28 23:08:54 +00:00
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/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
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/// corresponding live-in physical register.
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unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->second == VReg)
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return I->first;
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return 0;
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}
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2010-04-14 16:51:49 +00:00
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static cl::opt<bool>
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SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
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cl::desc("Schedule copies of livein registers"),
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cl::init(false));
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible.
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static void EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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DenseMap<MachineInstr*, unsigned> &CopyRegMap,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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unsigned NumUses = 0;
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MachineInstr *UseMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
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UE = MRI.use_end(); UI != UE; ++UI) {
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UseMI = &*UI;
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if (++NumUses > 1)
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break;
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}
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// If the number of uses is not one, or the use is not a move instruction,
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// don't coalesce. Also, only coalesce away a virtual register to virtual
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// register copy.
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bool Coalesced = false;
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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if (NumUses == 1 &&
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TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
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TargetRegisterInfo::isVirtualRegister(DstReg)) {
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VirtReg = DstReg;
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Coalesced = true;
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}
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// Now find an ideal location to insert the copy.
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MachineBasicBlock::iterator Pos = InsertPos;
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while (Pos != MBB->begin()) {
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MachineInstr *PrevMI = prior(Pos);
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DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
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// copyRegToReg might emit multiple instructions to do a copy.
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unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
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if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
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// This is what the BB looks like right now:
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// r1024 = mov r0
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// ...
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// r1 = mov r1024
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//
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// We want to insert "r1025 = mov r1". Inserting this copy below the
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// move to r1024 makes it impossible for that move to be coalesced.
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//
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// r1025 = mov r1
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// r1024 = mov r0
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// ...
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// r1 = mov 1024
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// r2 = mov 1025
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break; // Woot! Found a good location.
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--Pos;
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}
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bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
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assert(Emitted && "Unable to issue a live-in copy instruction!\n");
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(void) Emitted;
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CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
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if (Coalesced) {
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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}
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}
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// into the given entry block.
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void
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MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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if (SchedLiveInCopies) {
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// Emit the copies at a heuristically-determined location in the block.
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DenseMap<MachineInstr*, unsigned> CopyRegMap;
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MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
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for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
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E = livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = getRegClass(LI->second);
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EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
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RC, CopyRegMap, *this, TRI, TII);
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}
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} else {
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// Emit the copies into the top of the block.
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for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
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E = livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = getRegClass(LI->second);
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bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
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LI->second, LI->first, RC, RC);
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assert(Emitted && "Unable to issue a live-in copy instruction!\n");
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(void) Emitted;
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}
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}
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2010-04-14 17:05:00 +00:00
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// Add function live-ins to entry block live-in set.
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for (MachineRegisterInfo::livein_iterator I = livein_begin(),
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E = livein_end(); I != E; ++I)
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EntryMBB->addLiveIn(I->first);
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2010-04-14 16:51:49 +00:00
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}
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2008-02-13 02:45:38 +00:00
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#ifndef NDEBUG
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void MachineRegisterInfo::dumpUses(unsigned Reg) const {
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for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
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I.getOperand().getParent()->dump();
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}
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#endif
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