[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64
types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This
patch adds that support.
As with lxvd2x/stxvd2x, this involves straightforward overriding of
the patterns normally recognized for lvx/stvx, with preference given
to the VSX patterns when VSX is enabled.
In addition, the logic for permitting misaligned memory accesses is
modified so that v4r32 and v4i32 are treated the same as v2f64 and
v2i64 when VSX is enabled. Finally, the DAG generation for unaligned
loads is changed to just use a normal LOAD (which will become lxvw4x)
on P8 and later hardware, where unaligned loads are preferred over
lvsl/lvx/lvx/vperm.
A number of tests now generate the VSX loads/stores instead of
lvx/stvx, so this patch adds VSX variants to those tests. I've also
added <4 x float> tests to the vsx.ll test case, and created a
vsx-p8.ll test case to be used for testing code generation for the
P8Vector feature. For now, that simply tests the unaligned load/store
behavior.
This has been tested along with a temporary patch to enable the VSX
and P8Vector features, with no new regressions encountered with or
without the temporary patch applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-17 15:13:38 +00:00
|
|
|
; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s
|
2014-12-05 20:32:05 +00:00
|
|
|
; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s
|
|
|
|
|
; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s
|
|
|
|
|
; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
|
[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64
types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This
patch adds that support.
As with lxvd2x/stxvd2x, this involves straightforward overriding of
the patterns normally recognized for lvx/stvx, with preference given
to the VSX patterns when VSX is enabled.
In addition, the logic for permitting misaligned memory accesses is
modified so that v4r32 and v4i32 are treated the same as v2f64 and
v2i64 when VSX is enabled. Finally, the DAG generation for unaligned
loads is changed to just use a normal LOAD (which will become lxvw4x)
on P8 and later hardware, where unaligned loads are preferred over
lvsl/lvx/lvx/vperm.
A number of tests now generate the VSX loads/stores instead of
lvx/stvx, so this patch adds VSX variants to those tests. I've also
added <4 x float> tests to the vsx.ll test case, and created a
vsx-p8.ll test case to be used for testing code generation for the
P8Vector feature. For now, that simply tests the unaligned load/store
behavior.
This has been tested along with a temporary patch to enable the VSX
and P8Vector features, with no new regressions encountered with or
without the temporary patch applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-17 15:13:38 +00:00
|
|
|
target datalayout = "E-m:e-i64:64-n32:64"
|
|
|
|
|
target triple = "powerpc64-unknown-linux-gnu"
|
|
|
|
|
|
|
|
|
|
; Unaligned loads/stores on P8 and later should use VSX where possible.
|
|
|
|
|
|
|
|
|
|
define <2 x double> @test28u(<2 x double>* %a) {
|
|
|
|
|
%v = load <2 x double>* %a, align 8
|
|
|
|
|
ret <2 x double> %v
|
|
|
|
|
|
|
|
|
|
; CHECK-LABEL: @test28u
|
|
|
|
|
; CHECK: lxvd2x 34, 0, 3
|
|
|
|
|
; CHECK: blr
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @test29u(<2 x double>* %a, <2 x double> %b) {
|
|
|
|
|
store <2 x double> %b, <2 x double>* %a, align 8
|
|
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
; CHECK-LABEL: @test29u
|
|
|
|
|
; CHECK: stxvd2x 34, 0, 3
|
|
|
|
|
; CHECK: blr
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x float> @test32u(<4 x float>* %a) {
|
|
|
|
|
%v = load <4 x float>* %a, align 8
|
|
|
|
|
ret <4 x float> %v
|
|
|
|
|
|
2014-12-05 20:32:05 +00:00
|
|
|
; CHECK-REG-LABEL: @test32u
|
|
|
|
|
; CHECK-REG: lxvw4x 34, 0, 3
|
|
|
|
|
; CHECK-REG: blr
|
|
|
|
|
|
|
|
|
|
; CHECK-FISL-LABEL: @test32u
|
|
|
|
|
; CHECK-FISL: lxvw4x 0, 0, 3
|
|
|
|
|
; CHECK-FISL: xxlor 34, 0, 0
|
|
|
|
|
; CHECK-FISL: blr
|
[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64
types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This
patch adds that support.
As with lxvd2x/stxvd2x, this involves straightforward overriding of
the patterns normally recognized for lvx/stvx, with preference given
to the VSX patterns when VSX is enabled.
In addition, the logic for permitting misaligned memory accesses is
modified so that v4r32 and v4i32 are treated the same as v2f64 and
v2i64 when VSX is enabled. Finally, the DAG generation for unaligned
loads is changed to just use a normal LOAD (which will become lxvw4x)
on P8 and later hardware, where unaligned loads are preferred over
lvsl/lvx/lvx/vperm.
A number of tests now generate the VSX loads/stores instead of
lvx/stvx, so this patch adds VSX variants to those tests. I've also
added <4 x float> tests to the vsx.ll test case, and created a
vsx-p8.ll test case to be used for testing code generation for the
P8Vector feature. For now, that simply tests the unaligned load/store
behavior.
This has been tested along with a temporary patch to enable the VSX
and P8Vector features, with no new regressions encountered with or
without the temporary patch applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-17 15:13:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @test33u(<4 x float>* %a, <4 x float> %b) {
|
|
|
|
|
store <4 x float> %b, <4 x float>* %a, align 8
|
|
|
|
|
ret void
|
|
|
|
|
|
2014-12-05 20:32:05 +00:00
|
|
|
; CHECK-REG-LABEL: @test33u
|
|
|
|
|
; CHECK-REG: stxvw4x 34, 0, 3
|
|
|
|
|
; CHECK-REG: blr
|
|
|
|
|
|
|
|
|
|
; CHECK-FISL-LABEL: @test33u
|
|
|
|
|
; CHECK-FISL: vor 3, 2, 2
|
|
|
|
|
; CHECK-FISL: stxvw4x 35, 0, 3
|
|
|
|
|
; CHECK-FISL: blr
|
[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64
types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This
patch adds that support.
As with lxvd2x/stxvd2x, this involves straightforward overriding of
the patterns normally recognized for lvx/stvx, with preference given
to the VSX patterns when VSX is enabled.
In addition, the logic for permitting misaligned memory accesses is
modified so that v4r32 and v4i32 are treated the same as v2f64 and
v2i64 when VSX is enabled. Finally, the DAG generation for unaligned
loads is changed to just use a normal LOAD (which will become lxvw4x)
on P8 and later hardware, where unaligned loads are preferred over
lvsl/lvx/lvx/vperm.
A number of tests now generate the VSX loads/stores instead of
lvx/stvx, so this patch adds VSX variants to those tests. I've also
added <4 x float> tests to the vsx.ll test case, and created a
vsx-p8.ll test case to be used for testing code generation for the
P8Vector feature. For now, that simply tests the unaligned load/store
behavior.
This has been tested along with a temporary patch to enable the VSX
and P8Vector features, with no new regressions encountered with or
without the temporary patch applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-17 15:13:38 +00:00
|
|
|
}
|
|
|
|
|
|
