2013-05-03 19:50:27 +00:00
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
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# FIXME: Condition register bit symbols
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# Branch mnemonics
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# CHECK: blr # encoding: [0x4e,0x80,0x00,0x20]
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blr
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# CHECK: bctr # encoding: [0x4e,0x80,0x04,0x20]
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bctr
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2013-06-24 11:01:55 +00:00
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# CHECK: blrl # encoding: [0x4e,0x80,0x00,0x21]
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blrl
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2013-05-03 19:50:27 +00:00
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# CHECK: bctrl # encoding: [0x4e,0x80,0x04,0x21]
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bctrl
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# FIXME: bt 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bt target
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2013-05-03 19:50:27 +00:00
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# FIXME: bta 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bta target
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2013-05-03 19:50:27 +00:00
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# FIXME: btlr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: btlr
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2013-05-03 19:50:27 +00:00
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# FIXME: btctr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: btctr
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2013-05-03 19:50:27 +00:00
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# FIXME: btl 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: btl target
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2013-05-03 19:50:27 +00:00
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# FIXME: btla 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: btla target
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2013-05-03 19:50:27 +00:00
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# FIXME: btlrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: btlrl
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2013-05-03 19:50:27 +00:00
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# FIXME: btctrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: btctrl
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2013-05-03 19:50:27 +00:00
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# FIXME: bf 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bf target
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2013-05-03 19:50:27 +00:00
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# FIXME: bfa 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bfa target
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2013-05-03 19:50:27 +00:00
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# FIXME: bflr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bflr
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2013-05-03 19:50:27 +00:00
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# FIXME: bfctr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bfctr
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2013-05-03 19:50:27 +00:00
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# FIXME: bfl 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bfl target
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2013-05-03 19:50:27 +00:00
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# FIXME: bfla 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bfla target
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2013-05-03 19:50:27 +00:00
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# FIXME: bflrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bflrl
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2013-05-03 19:50:27 +00:00
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# FIXME: bfctrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bfctrl
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2013-05-03 19:50:27 +00:00
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# CHECK: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bdnz target
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2013-06-24 11:03:33 +00:00
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# CHECK: bdnza target # encoding: [0x42,0x00,A,0bAAAAAA10]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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bdnza target
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2013-05-03 19:50:27 +00:00
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# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20]
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bdnzlr
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2013-06-24 11:02:38 +00:00
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# CHECK: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bdnzl target
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2013-06-24 11:03:33 +00:00
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# CHECK: bdnzla target # encoding: [0x42,0x00,A,0bAAAAAA11]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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bdnzla target
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2013-06-24 11:02:38 +00:00
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# CHECK: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21]
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bdnzlrl
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzt 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzt target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzta 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzta target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnztlr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnztlr
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnztl 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnztl target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnztla 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnztla target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnztlrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnztlrl
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzf 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzf target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzfa 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzfa target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzflr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzflr
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzfl 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzfl target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzfla 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzfla target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdnzflrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdnzflrl
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2013-05-03 19:50:27 +00:00
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# CHECK: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bdz target
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2013-06-24 11:03:33 +00:00
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# CHECK: bdza target # encoding: [0x42,0x40,A,0bAAAAAA10]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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bdza target
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2013-05-03 19:50:27 +00:00
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# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20]
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bdzlr
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2013-06-24 11:02:38 +00:00
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# CHECK: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bdzl target
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2013-06-24 11:03:33 +00:00
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# CHECK: bdzla target # encoding: [0x42,0x40,A,0bAAAAAA11]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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bdzla target
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2013-06-24 11:02:38 +00:00
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# CHECK: bdzlrl # encoding: [0x4e,0x40,0x00,0x21]
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bdzlrl
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2013-06-10 17:19:15 +00:00
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzt 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzt target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzta 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzta target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdztlr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdztlr
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2013-05-03 19:50:27 +00:00
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# FIXME: bdztl 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdztl target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdztla 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdztla target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdztlrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdztlrl
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzf 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzf target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzfa 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzfa target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzflr 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzflr
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzfl 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzfl target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzfla 2, target
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzfla target
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2013-05-03 19:50:27 +00:00
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# FIXME: bdzflrl 2
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2013-06-10 17:19:15 +00:00
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# FIXME: bdzflrl
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2013-05-03 19:50:27 +00:00
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# CHECK: blt 2, target # encoding: [0x41,0x88,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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blt 2, target
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2013-06-10 17:19:15 +00:00
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# CHECK: blt 0, target # encoding: [0x41,0x80,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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blt target
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2013-06-24 11:03:33 +00:00
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# CHECK: blta 2, target # encoding: [0x41,0x88,A,0bAAAAAA10]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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blta 2, target
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# CHECK: blta 0, target # encoding: [0x41,0x80,A,0bAAAAAA10]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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blta target
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2013-05-03 19:50:27 +00:00
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# CHECK: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20]
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bltlr 2
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2013-06-10 17:19:15 +00:00
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# CHECK: bltlr 0 # encoding: [0x4d,0x80,0x00,0x20]
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bltlr
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2013-05-03 19:50:27 +00:00
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# CHECK: bltctr 2 # encoding: [0x4d,0x88,0x04,0x20]
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bltctr 2
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2013-06-10 17:19:15 +00:00
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# CHECK: bltctr 0 # encoding: [0x4d,0x80,0x04,0x20]
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bltctr
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2013-06-24 11:02:19 +00:00
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# CHECK: bltl 2, target # encoding: [0x41,0x88,A,0bAAAAAA01]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bltl 2, target
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# CHECK: bltl 0, target # encoding: [0x41,0x80,A,0bAAAAAA01]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bltl target
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2013-06-24 11:03:33 +00:00
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# CHECK: bltla 2, target # encoding: [0x41,0x88,A,0bAAAAAA11]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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bltla 2, target
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# CHECK: bltla 0, target # encoding: [0x41,0x80,A,0bAAAAAA11]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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bltla target
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2013-06-24 11:01:55 +00:00
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# CHECK: bltlrl 2 # encoding: [0x4d,0x88,0x00,0x21]
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bltlrl 2
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# CHECK: bltlrl 0 # encoding: [0x4d,0x80,0x00,0x21]
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bltlrl
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2013-05-03 19:50:27 +00:00
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# CHECK: bltctrl 2 # encoding: [0x4d,0x88,0x04,0x21]
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bltctrl 2
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2013-06-10 17:19:15 +00:00
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# CHECK: bltctrl 0 # encoding: [0x4d,0x80,0x04,0x21]
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bltctrl
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2013-05-03 19:50:27 +00:00
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# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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ble 2, target
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2013-06-10 17:19:15 +00:00
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# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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ble target
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2013-06-24 11:03:33 +00:00
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# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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blea 2, target
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# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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blea target
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2013-05-03 19:50:27 +00:00
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# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
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blelr 2
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2013-06-10 17:19:15 +00:00
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# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20]
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blelr
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2013-05-03 19:50:27 +00:00
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# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20]
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blectr 2
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2013-06-10 17:19:15 +00:00
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# CHECK: blectr 0 # encoding: [0x4c,0x81,0x04,0x20]
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blectr
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2013-06-24 11:02:19 +00:00
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# CHECK: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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blel 2, target
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# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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blel target
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2013-06-24 11:03:33 +00:00
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# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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blela 2, target
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# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
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blela target
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2013-06-24 11:01:55 +00:00
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# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21]
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blelrl 2
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# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21]
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blelrl
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2013-05-03 19:50:27 +00:00
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# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21]
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blectrl 2
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2013-06-10 17:19:15 +00:00
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# CHECK: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21]
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blectrl
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2013-05-03 19:50:27 +00:00
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# CHECK: beq 2, target # encoding: [0x41,0x8a,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
beq 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
beq target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: beqa 2, target # encoding: [0x41,0x8a,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
beqa 2, target
|
|
|
|
|
# CHECK: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
beqa target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20]
|
|
|
|
|
beqlr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20]
|
|
|
|
|
beqlr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: beqctr 2 # encoding: [0x4d,0x8a,0x04,0x20]
|
|
|
|
|
beqctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: beqctr 0 # encoding: [0x4d,0x82,0x04,0x20]
|
|
|
|
|
beqctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: beql 2, target # encoding: [0x41,0x8a,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
beql 2, target
|
|
|
|
|
# CHECK: beql 0, target # encoding: [0x41,0x82,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
beql target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: beqla 2, target # encoding: [0x41,0x8a,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
beqla 2, target
|
|
|
|
|
# CHECK: beqla 0, target # encoding: [0x41,0x82,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
beqla target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: beqlrl 2 # encoding: [0x4d,0x8a,0x00,0x21]
|
|
|
|
|
beqlrl 2
|
|
|
|
|
# CHECK: beqlrl 0 # encoding: [0x4d,0x82,0x00,0x21]
|
|
|
|
|
beqlrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: beqctrl 2 # encoding: [0x4d,0x8a,0x04,0x21]
|
|
|
|
|
beqctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: beqctrl 0 # encoding: [0x4d,0x82,0x04,0x21]
|
|
|
|
|
beqctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bge 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bge target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgea 2, target
|
|
|
|
|
# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgea target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
|
|
|
|
|
bgelr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20]
|
|
|
|
|
bgelr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20]
|
|
|
|
|
bgectr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20]
|
|
|
|
|
bgectr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bgel 2, target
|
|
|
|
|
# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bgel target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgela 2, target
|
|
|
|
|
# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgela target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21]
|
|
|
|
|
bgelrl 2
|
|
|
|
|
# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21]
|
|
|
|
|
bgelrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21]
|
|
|
|
|
bgectrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21]
|
|
|
|
|
bgectrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bgt 2, target # encoding: [0x41,0x89,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bgt 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgt 0, target # encoding: [0x41,0x81,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bgt target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bgta 2, target # encoding: [0x41,0x89,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgta 2, target
|
|
|
|
|
# CHECK: bgta 0, target # encoding: [0x41,0x81,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgta target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20]
|
|
|
|
|
bgtlr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgtlr 0 # encoding: [0x4d,0x81,0x00,0x20]
|
|
|
|
|
bgtlr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgtctr 2 # encoding: [0x4d,0x89,0x04,0x20]
|
|
|
|
|
bgtctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgtctr 0 # encoding: [0x4d,0x81,0x04,0x20]
|
|
|
|
|
bgtctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bgtl 2, target # encoding: [0x41,0x89,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bgtl 2, target
|
|
|
|
|
# CHECK: bgtl 0, target # encoding: [0x41,0x81,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bgtl target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bgtla 2, target # encoding: [0x41,0x89,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgtla 2, target
|
|
|
|
|
# CHECK: bgtla 0, target # encoding: [0x41,0x81,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bgtla target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bgtlrl 2 # encoding: [0x4d,0x89,0x00,0x21]
|
|
|
|
|
bgtlrl 2
|
|
|
|
|
# CHECK: bgtlrl 0 # encoding: [0x4d,0x81,0x00,0x21]
|
|
|
|
|
bgtlrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgtctrl 2 # encoding: [0x4d,0x89,0x04,0x21]
|
|
|
|
|
bgtctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgtctrl 0 # encoding: [0x4d,0x81,0x04,0x21]
|
|
|
|
|
bgtctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnl 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnl target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnla 2, target
|
|
|
|
|
# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnla target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
|
|
|
|
|
bnllr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20]
|
|
|
|
|
bnllr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20]
|
|
|
|
|
bnlctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20]
|
|
|
|
|
bnlctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnll 2, target
|
|
|
|
|
# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnll target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnlla 2, target
|
|
|
|
|
# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnlla target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21]
|
|
|
|
|
bnllrl 2
|
|
|
|
|
# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21]
|
|
|
|
|
bnllrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21]
|
|
|
|
|
bnlctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21]
|
|
|
|
|
bnlctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bne 2, target # encoding: [0x40,0x8a,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bne 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bne 0, target # encoding: [0x40,0x82,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bne target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bnea 2, target # encoding: [0x40,0x8a,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnea 2, target
|
|
|
|
|
# CHECK: bnea 0, target # encoding: [0x40,0x82,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnea target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20]
|
|
|
|
|
bnelr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnelr 0 # encoding: [0x4c,0x82,0x00,0x20]
|
|
|
|
|
bnelr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnectr 2 # encoding: [0x4c,0x8a,0x04,0x20]
|
|
|
|
|
bnectr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnectr 0 # encoding: [0x4c,0x82,0x04,0x20]
|
|
|
|
|
bnectr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bnel 2, target # encoding: [0x40,0x8a,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnel 2, target
|
|
|
|
|
# CHECK: bnel 0, target # encoding: [0x40,0x82,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnel target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bnela 2, target # encoding: [0x40,0x8a,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnela 2, target
|
|
|
|
|
# CHECK: bnela 0, target # encoding: [0x40,0x82,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnela target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bnelrl 2 # encoding: [0x4c,0x8a,0x00,0x21]
|
|
|
|
|
bnelrl 2
|
|
|
|
|
# CHECK: bnelrl 0 # encoding: [0x4c,0x82,0x00,0x21]
|
|
|
|
|
bnelrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnectrl 2 # encoding: [0x4c,0x8a,0x04,0x21]
|
|
|
|
|
bnectrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnectrl 0 # encoding: [0x4c,0x82,0x04,0x21]
|
|
|
|
|
bnectrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bng 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bng target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnga 2, target
|
|
|
|
|
# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnga target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
|
|
|
|
|
bnglr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20]
|
|
|
|
|
bnglr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20]
|
|
|
|
|
bngctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: blectr 0 # encoding: [0x4c,0x81,0x04,0x20]
|
|
|
|
|
bngctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bngl 2, target
|
|
|
|
|
# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bngl target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bngla 2, target
|
|
|
|
|
# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bngla target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21]
|
|
|
|
|
bnglrl 2
|
|
|
|
|
# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21]
|
|
|
|
|
bnglrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21]
|
|
|
|
|
bngctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21]
|
|
|
|
|
bngctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bso 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bso target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bsoa 2, target
|
|
|
|
|
# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bsoa target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
|
|
|
|
|
bsolr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20]
|
|
|
|
|
bsolr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20]
|
|
|
|
|
bsoctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20]
|
|
|
|
|
bsoctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bsol 2, target
|
|
|
|
|
# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bsol target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bsola 2, target
|
|
|
|
|
# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bsola target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21]
|
|
|
|
|
bsolrl 2
|
|
|
|
|
# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21]
|
|
|
|
|
bsolrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21]
|
|
|
|
|
bsoctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21]
|
|
|
|
|
bsoctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bns 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bns target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnsa 2, target
|
|
|
|
|
# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnsa target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
|
|
|
|
|
bnslr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20]
|
|
|
|
|
bnslr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20]
|
|
|
|
|
bnsctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20]
|
|
|
|
|
bnsctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnsl 2, target
|
|
|
|
|
# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnsl target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnsla 2, target
|
|
|
|
|
# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnsla target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21]
|
|
|
|
|
bnslrl 2
|
|
|
|
|
# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21]
|
|
|
|
|
bnslrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21]
|
|
|
|
|
bnsctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21]
|
|
|
|
|
bnsctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bun 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bun target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
buna 2, target
|
|
|
|
|
# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
buna target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
|
|
|
|
|
bunlr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20]
|
|
|
|
|
bunlr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20]
|
|
|
|
|
bunctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20]
|
|
|
|
|
bunctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bunl 2, target
|
|
|
|
|
# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bunl target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bunla 2, target
|
|
|
|
|
# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bunla target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21]
|
|
|
|
|
bunlrl 2
|
|
|
|
|
# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21]
|
|
|
|
|
bunlrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21]
|
|
|
|
|
bunctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21]
|
|
|
|
|
bunctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnu 2, target
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnu target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnua 2, target
|
|
|
|
|
# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnua target
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
|
|
|
|
|
bnulr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20]
|
|
|
|
|
bnulr
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20]
|
|
|
|
|
bnuctr 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20]
|
|
|
|
|
bnuctr
|
2013-06-24 11:02:19 +00:00
|
|
|
# CHECK: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnul 2, target
|
|
|
|
|
# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
|
|
|
|
bnul target
|
2013-06-24 11:03:33 +00:00
|
|
|
# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnula 2, target
|
|
|
|
|
# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
|
|
|
|
|
bnula target
|
2013-06-24 11:01:55 +00:00
|
|
|
# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21]
|
|
|
|
|
bnulrl 2
|
|
|
|
|
# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21]
|
|
|
|
|
bnulrl
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21]
|
|
|
|
|
bnuctrl 2
|
2013-06-10 17:19:15 +00:00
|
|
|
# CHECK: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21]
|
|
|
|
|
bnuctrl
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# FIXME: Condition register logical mnemonics
|
|
|
|
|
|
|
|
|
|
# FIXME: Subtract mnemonics
|
|
|
|
|
|
|
|
|
|
# Compare mnemonics
|
|
|
|
|
|
|
|
|
|
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
|
|
|
|
|
cmpdi 2, 3, 128
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
|
|
|
|
|
cmpdi 3, 128
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
|
|
|
|
|
cmpd 2, 3, 4
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
|
|
|
|
|
cmpd 3, 4
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
|
|
|
|
|
cmpldi 2, 3, 128
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
|
|
|
|
|
cmpldi 3, 128
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
|
|
|
|
|
cmpld 2, 3, 4
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
|
|
|
|
|
cmpld 3, 4
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
|
|
|
|
|
cmpwi 2, 3, 128
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
|
|
|
|
|
cmpwi 3, 128
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
|
|
|
|
|
cmpw 2, 3, 4
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
|
|
|
|
|
cmpw 3, 4
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
|
|
|
|
|
cmplwi 2, 3, 128
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
|
|
|
|
|
cmplwi 3, 128
|
2013-05-03 19:50:27 +00:00
|
|
|
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
|
|
|
|
|
cmplw 2, 3, 4
|
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 16:15:12 +00:00
|
|
|
# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
|
|
|
|
|
cmplw 3, 4
|
2013-05-03 19:50:27 +00:00
|
|
|
|
|
|
|
|
# FIXME: Trap mnemonics
|
|
|
|
|
|
|
|
|
|
# Rotate and shift mnemonics
|
|
|
|
|
|
|
|
|
|
# FIXME: extldi 2, 3, 4, 5
|
|
|
|
|
# FIXME: extrdi 2, 3, 4, 5
|
|
|
|
|
# FIXME: insrdi 2, 3, 4, 5
|
|
|
|
|
# FIXME: rotldi 2, 3, 4
|
|
|
|
|
# FIXME: rotrdi 2, 3, 4
|
|
|
|
|
# FIXME: rotld 2, 3, 4
|
|
|
|
|
# CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4]
|
|
|
|
|
sldi 2, 3, 4
|
|
|
|
|
# CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02]
|
|
|
|
|
srdi 2, 3, 4
|
|
|
|
|
# FIXME: clrldi 2, 3, 4
|
|
|
|
|
# FIXME: clrrdi 2, 3, 4
|
|
|
|
|
# FIXME: clrlsldi 2, 3, 4, 5
|
|
|
|
|
|
|
|
|
|
# FIXME: extlwi 2, 3, 4, 5
|
|
|
|
|
# FIXME: extrwi 2, 3, 4, 5
|
|
|
|
|
# FIXME: inslwi 2, 3, 4, 5
|
|
|
|
|
# FIXME: insrwi 2, 3, 4, 5
|
|
|
|
|
# FIXME: rotlwi 2, 3, 4
|
|
|
|
|
# FIXME: rotrwi 2, 3, 4
|
|
|
|
|
# FIXME: rotlw 2, 3, 4
|
|
|
|
|
# CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36]
|
|
|
|
|
slwi 2, 3, 4
|
|
|
|
|
# CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e]
|
|
|
|
|
srwi 2, 3, 4
|
|
|
|
|
# FIXME: clrlwi 2, 3, 4
|
|
|
|
|
# FIXME: clrrwi 2, 3, 4
|
|
|
|
|
# FIXME: clrlslwi 2, 3, 4, 5
|
|
|
|
|
|
|
|
|
|
# Move to/from special purpose register mnemonics
|
|
|
|
|
|
|
|
|
|
# FIXME: mtxer 2
|
|
|
|
|
# FIXME: mfxer 2
|
|
|
|
|
# CHECK: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6]
|
|
|
|
|
mtlr 2
|
|
|
|
|
# CHECK: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6]
|
|
|
|
|
mflr 2
|
|
|
|
|
# CHECK: mtctr 2 # encoding: [0x7c,0x49,0x03,0xa6]
|
|
|
|
|
mtctr 2
|
|
|
|
|
# CHECK: mfctr 2 # encoding: [0x7c,0x49,0x02,0xa6]
|
|
|
|
|
mfctr 2
|
|
|
|
|
|
|
|
|
|
# Miscellaneous mnemonics
|
|
|
|
|
|
|
|
|
|
# CHECK: nop # encoding: [0x60,0x00,0x00,0x00]
|
|
|
|
|
nop
|
|
|
|
|
# FIXME: xnop
|
|
|
|
|
# CHECK: li 2, 128 # encoding: [0x38,0x40,0x00,0x80]
|
|
|
|
|
li 2, 128
|
|
|
|
|
# CHECK: lis 2, 128 # encoding: [0x3c,0x40,0x00,0x80]
|
|
|
|
|
lis 2, 128
|
|
|
|
|
# FIXME: la 2, 128(4)
|
|
|
|
|
# CHECK: mr 2, 3 # encoding: [0x7c,0x62,0x1b,0x78]
|
|
|
|
|
mr 2, 3
|
|
|
|
|
# FIXME: not 2, 3
|
|
|
|
|
|