2009-10-27 05:50:28 +00:00
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; RUN: llc < %s -march=arm | FileCheck %s
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2009-06-25 20:59:23 +00:00
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define i64 @f1(i64 %a, i64 %b) {
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2013-07-14 06:24:09 +00:00
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; CHECK-LABEL: f1:
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2009-10-27 05:50:28 +00:00
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; CHECK: subs r
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; CHECK: sbc r
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2009-06-25 20:59:23 +00:00
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entry:
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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2013-07-14 06:24:09 +00:00
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; CHECK-LABEL: f2:
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2009-10-27 05:50:28 +00:00
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; CHECK: adc r
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; CHECK: subs r
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; CHECK: sbc r
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2009-06-25 20:59:23 +00:00
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entry:
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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2011-04-23 03:55:32 +00:00
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; add with live carry
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define i64 @f3(i32 %al, i32 %bl) {
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2013-07-14 06:24:09 +00:00
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; CHECK-LABEL: f3:
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2011-04-23 03:55:32 +00:00
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; CHECK: adds r
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; CHECK: adc r
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entry:
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; unsigned wide add
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%aw = zext i32 %al to i64
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%bw = zext i32 %bl to i64
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%cw = add i64 %aw, %bw
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; ch == carry bit
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%ch = lshr i64 %cw, 32
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%dw = add i64 %ch, %bw
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ret i64 %dw
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}
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2011-09-06 18:52:20 +00:00
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; rdar://10073745
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define i64 @f4(i64 %x) nounwind readnone {
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entry:
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2013-07-14 06:24:09 +00:00
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; CHECK-LABEL: f4:
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2011-09-06 18:52:20 +00:00
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; CHECK: rsbs r
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; CHECK: rsc r
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%0 = sub nsw i64 0, %x
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ret i64 %0
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}
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2012-10-24 19:53:01 +00:00
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; rdar://12559385
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define i64 @f5(i32 %vi) {
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entry:
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2013-07-14 06:24:09 +00:00
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; CHECK-LABEL: f5:
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2012-10-24 19:53:01 +00:00
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; CHECK: movw [[REG:r[0-9]+]], #36102
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; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
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%v0 = zext i32 %vi to i64
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%v1 = xor i64 %v0, -155057456198619
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%v4 = add i64 %v1, 155057456198619
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%v5 = add i64 %v4, %v1
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ret i64 %v5
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}
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