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//===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
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2005-04-22 00:00:37 +00:00
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//
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2004-08-01 05:04:00 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:37:13 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 00:00:37 +00:00
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//
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2004-08-01 05:04:00 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This file defines a wrapper class for the 'Instruction' TableGen class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_INSTRUCTION_H
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#define CODEGEN_INSTRUCTION_H
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#include "llvm/CodeGen/ValueTypes.h"
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#include <string>
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#include <vector>
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#include <utility>
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namespace llvm {
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class Record;
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class DagInit;
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class CodeGenInstruction {
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public:
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Record *TheDef; // The actual record defining this instruction.
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std::string Namespace; // The namespace the instruction is in.
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/// AsmString - The format string used to emit a .s file for the
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/// instruction.
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std::string AsmString;
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/// OperandInfo - The information we keep track of for each operand in the
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/// operand list for a tablegen instruction.
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struct OperandInfo {
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/// Rec - The definition this operand is declared as.
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///
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Record *Rec;
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/// Name - If this operand was assigned a symbolic name, this is it,
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/// otherwise, it's empty.
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std::string Name;
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/// PrinterMethodName - The method used to print operands of this type in
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/// the asmprinter.
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std::string PrinterMethodName;
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/// MIOperandNo - Currently (this is meant to be phased out), some logical
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/// operands correspond to multiple MachineInstr operands. In the X86
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/// target for example, one address operand is represented as 4
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/// MachineOperands. Because of this, the operand number in the
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/// OperandList may not match the MachineInstr operand num. Until it
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/// does, this contains the MI operand index of this operand.
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unsigned MIOperandNo;
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unsigned MINumOperands; // The number of operands.
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/// DoNotEncode - Bools are set to true in this vector for each operand in
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/// the DisableEncoding list. These should not be emitted by the code
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/// emitter.
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std::vector<bool> DoNotEncode;
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/// MIOperandInfo - Default MI operand type. Note an operand may be made
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/// up of multiple MI operands.
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DagInit *MIOperandInfo;
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/// Constraint info for this operand. This operand can have pieces, so we
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/// track constraint info for each.
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std::vector<std::string> Constraints;
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OperandInfo(Record *R, const std::string &N, const std::string &PMN,
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unsigned MION, unsigned MINO, DagInit *MIOI)
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: Rec(R), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
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MINumOperands(MINO), MIOperandInfo(MIOI) {}
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};
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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/// NumDefs - Number of def operands declared.
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///
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unsigned NumDefs;
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/// OperandList - The list of declared operands, along with their declared
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/// type (which is a record).
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std::vector<OperandInfo> OperandList;
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// Various boolean values we track for the instruction.
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bool isReturn;
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bool isBranch;
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bool isIndirectBranch;
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bool isBarrier;
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bool isCall;
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bool canFoldAsLoad;
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bool mayLoad, mayStore;
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bool isPredicable;
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bool isConvertibleToThreeAddress;
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bool isCommutable;
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bool isTerminator;
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bool isReMaterializable;
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bool hasDelaySlot;
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bool usesCustomDAGSchedInserter;
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bool isVariadic;
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bool hasCtrlDep;
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bool isNotDuplicable;
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bool hasOptionalDef;
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bool hasSideEffects;
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bool mayHaveSideEffects;
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bool neverHasSideEffects;
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bool isAsCheapAsAMove;
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/// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
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/// where $foo is a whole operand and $foo.bar refers to a suboperand.
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/// This throws an exception if the name is invalid. If AllowWholeOp is
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/// true, references to operands with suboperands are allowed, otherwise
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/// not.
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std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
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bool AllowWholeOp = true);
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/// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
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/// flat machineinstr operand #.
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unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
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return OperandList[Op.first].MIOperandNo + Op.second;
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}
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/// getSubOperandNumber - Unflatten a operand number into an
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/// operand/suboperand pair.
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std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
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for (unsigned i = 0; ; ++i) {
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assert(i < OperandList.size() && "Invalid flat operand #");
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if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
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return std::make_pair(i, Op-OperandList[i].MIOperandNo);
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}
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}
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/// isFlatOperandNotEmitted - Return true if the specified flat operand #
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/// should not be emitted with the code emitter.
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bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
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std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo);
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if (OperandList[Op.first].DoNotEncode.size() > Op.second)
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return OperandList[Op.first].DoNotEncode[Op.second];
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return false;
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}
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CodeGenInstruction(Record *R, const std::string &AsmStr);
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/// getOperandNamed - Return the index of the operand with the specified
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/// non-empty name. If the instruction does not have an operand with the
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/// specified name, throw an exception.
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unsigned getOperandNamed(const std::string &Name) const;
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};
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}
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#endif
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