6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-02 02:29:04 +00:00
parent 15f63ad2e5
commit aad75aa1a2
3 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
utils/TableGen/CodeGenInstruction.h
View File

@ -74,6 +74,8 @@ namespace llvm {
bool isLoad;
bool isStore;
bool isTwoAddress;
bool isConvertibleToThreeAddress;
bool isCommutable;
bool isTerminator;
bool hasDelaySlot;

2
utils/TableGen/CodeGenTarget.cpp
View File

@ -217,6 +217,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isLoad = R->getValueAsBit("isLoad");
isStore = R->getValueAsBit("isStore");
isTwoAddress = R->getValueAsBit("isTwoAddress");
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
isCommutable = R->getValueAsBit("isCommutable");
isTerminator = R->getValueAsBit("isTerminator");
hasDelaySlot = R->getValueAsBit("hasDelaySlot");

2
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -116,6 +116,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isLoad) OS << "|M_LOAD_FLAG";
if (Inst.isStore) OS << "|M_STORE_FLAG";
if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
OS << ", 0";