2007-06-06 07:42:06 +00:00
|
|
|
//===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
2008-02-10 18:45:23 +00:00
|
|
|
// This file contains the Mips implementation of the TargetRegisterInfo class.
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef MIPSREGISTERINFO_H
|
|
|
|
#define MIPSREGISTERINFO_H
|
|
|
|
|
2008-07-14 14:42:54 +00:00
|
|
|
#include "Mips.h"
|
2008-02-10 18:45:23 +00:00
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2007-06-06 07:42:06 +00:00
|
|
|
#include "MipsGenRegisterInfo.h.inc"
|
|
|
|
|
|
|
|
namespace llvm {
|
2008-07-14 14:42:54 +00:00
|
|
|
class MipsSubtarget;
|
2007-06-06 07:42:06 +00:00
|
|
|
class TargetInstrInfo;
|
|
|
|
class Type;
|
|
|
|
|
|
|
|
struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
2008-07-14 14:42:54 +00:00
|
|
|
const MipsSubtarget &Subtarget;
|
2007-06-06 07:42:06 +00:00
|
|
|
const TargetInstrInfo &TII;
|
|
|
|
|
2008-07-14 14:42:54 +00:00
|
|
|
MipsRegisterInfo(const MipsSubtarget &Subtarget, const TargetInstrInfo &tii);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2007-08-28 05:13:42 +00:00
|
|
|
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
|
|
|
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
|
|
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
|
|
|
|
2008-07-14 14:42:54 +00:00
|
|
|
/// Get PIC indirect call register
|
|
|
|
static unsigned getPICCallReg(void);
|
|
|
|
|
2008-08-06 06:14:43 +00:00
|
|
|
/// Adjust the Mips stack frame.
|
|
|
|
void adjustMipsStackFrame(MachineFunction &MF) const;
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
/// Code Generation virtual methods...
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
const TargetRegisterClass* const*
|
|
|
|
getCalleeSavedRegClasses(const MachineFunction* MF = 0) const;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
|
|
|
|
bool hasFP(const MachineFunction &MF) const;
|
|
|
|
|
|
|
|
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
|
2007-08-28 05:13:42 +00:00
|
|
|
/// Stack Frame Processing Methods
|
2007-06-06 07:42:06 +00:00
|
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
|
|
int SPAdj, RegScavenger *RS = NULL) const;
|
|
|
|
|
|
|
|
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
|
|
|
|
|
|
|
|
void emitPrologue(MachineFunction &MF) const;
|
|
|
|
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
|
|
|
|
2007-08-28 05:13:42 +00:00
|
|
|
/// Debug information queries.
|
2007-06-06 07:42:06 +00:00
|
|
|
unsigned getRARegister() const;
|
|
|
|
unsigned getFrameRegister(MachineFunction &MF) const;
|
|
|
|
|
2007-08-28 05:13:42 +00:00
|
|
|
/// Exception handling queries.
|
2007-06-06 07:42:06 +00:00
|
|
|
unsigned getEHExceptionRegister() const;
|
|
|
|
unsigned getEHHandlerRegister() const;
|
2007-11-11 19:50:10 +00:00
|
|
|
|
2007-11-13 19:13:01 +00:00
|
|
|
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
|
2007-06-06 07:42:06 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm
|
|
|
|
|
|
|
|
#endif
|