llvm-6502/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll

; RUN: llc < %s -march=x86-64
; PR4669
declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)

define <1 x i64> @test(i64 %t) {
entry:
	%t1 = insertelement <1 x i64> undef, i64 %t, i32 0
        %t0 = bitcast <1 x i64> %t1 to x86_mmx
	%t2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %t0, i32 48)
        %t3 = bitcast x86_mmx %t2 to <1 x i64>
	ret <1 x i64> %t3
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-08 23:54:48 +00:00			`; RUN: llc < %s -march=x86-64`
Use movq to move 64 bits in and out of mmx registers. Fixes PR4669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-03 02:45:34 +00:00			`; PR4669`
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8 2010-09-30 23:57:10 +00:00			`declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)`
Use movq to move 64 bits in and out of mmx registers. Fixes PR4669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-03 02:45:34 +00:00
			`define <1 x i64> @test(i64 %t) {`
			`entry:`
			`%t1 = insertelement <1 x i64> undef, i64 %t, i32 0`
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8 2010-09-30 23:57:10 +00:00			`%t0 = bitcast <1 x i64> %t1 to x86_mmx`
			`%t2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %t0, i32 48)`
			`%t3 = bitcast x86_mmx %t2 to <1 x i64>`
			`ret <1 x i64> %t3`
Use movq to move 64 bits in and out of mmx registers. Fixes PR4669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-03 02:45:34 +00:00			`}`