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llvm-6502/lib/Target/X86/Makefile

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We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
Added LLVM copyright notice to Makefiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9312 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 22:26:57 +00:00
#
# The LLVM Compiler Infrastructure
#
# This file was developed by the LLVM research group and is distributed under
# the University of Illinois Open Source License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
LEVEL = ../../..
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
# Make sure that tblgen is run, first thing.
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
Tablgen files for really simple instruction selector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 19:34:00 +00:00
X86GenInstrInfo.inc X86GenSimpInstrSelector.inc \
X86GenInstrSelector.inc
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Hopefully fix the objdir != srcdir issue git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9761 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-07 00:34:33 +00:00
X86GenRegisterNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
@echo "Building X86.td register names with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Hopefully fix the objdir != srcdir issue git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9761 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-07 00:34:33 +00:00
X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
@echo "Building X86.td register information header with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Hopefully fix the objdir != srcdir issue git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9761 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-07 00:34:33 +00:00
X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
@echo "Building X86.td register information implementation with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Hopefully fix the objdir != srcdir issue git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9761 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-07 00:34:33 +00:00
X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
@echo "Building X86.td instruction names with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
Hopefully fix the objdir != srcdir issue git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9761 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-07 00:34:33 +00:00
X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
@echo "Building X86.td instruction information with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
Tablgen files for really simple instruction selector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 19:34:00 +00:00
X86GenSimpInstrSelector.inc:: $(SourceDir)/X86InstrSel.td $(TBLGEN)
@echo "Building X86.td simple instruction selector with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-simp-instr-sel -o $@
Hopefully fix the objdir != srcdir issue git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9761 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-07 00:34:33 +00:00
X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
@echo "Building X86.td instruction selector with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
Tablgen files for really simple instruction selector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 19:34:00 +00:00
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
clean::
$(VERB) rm -f *.inc
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