llvm-6502/test/CodeGen/Hexagon/args.ll

; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s | FileCheck %s
; CHECK: r[[T0:[0-9]+]] = #7
; CHECK: memw(r29 + #0) = r[[T0]]
; CHECK: r0 = #1
; CHECK: r1 = #2
; CHECK: r2 = #3
; CHECK: r3 = #4
; CHECK: r4 = #5
; CHECK: r5 = #6


define void @foo() nounwind {
entry:
  call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
  ret void
}

declare void @bar(i32, i32, i32, i32, i32, i32, i32)
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8 2012-02-01 22:13:57 +00:00			`; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s \| FileCheck %s`
Hexagon backend support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8 2011-12-12 21:14:40 +00:00			`; CHECK: r[[T0:[0-9]+]] = #7`
			`; CHECK: memw(r29 + #0) = r[[T0]]`
			`; CHECK: r0 = #1`
			`; CHECK: r1 = #2`
			`; CHECK: r2 = #3`
			`; CHECK: r3 = #4`
			`; CHECK: r4 = #5`
			`; CHECK: r5 = #6`


			`define void @foo() nounwind {`
			`entry:`
			`call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)`
			`ret void`
			`}`

			`declare void @bar(i32, i32, i32, i32, i32, i32, i32)`