llvm-6502/test/CodeGen/ARM/smml.ll

; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s

define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
entry:
; CHECK-NOT: smmls
  %conv4 = zext i32 %a to i64
  %conv1 = sext i32 %b to i64
  %conv2 = sext i32 %c to i64
  %mul = mul nsw i64 %conv2, %conv1
  %shr5 = lshr i64 %mul, 32
  %sub = sub nsw i64 %conv4, %shr5
  %conv3 = trunc i64 %sub to i32
  ret i32 %conv3
}
ARM: update even more tests More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-03 17:35:22 +00:00			`; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \| FileCheck %s`

Remove incorrect pattern for ARM SMML instruction. Patch by Meador Inge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156989 91177308-0d34-0410-b5e6-96231b3b80d8 2012-05-17 13:12:13 +00:00			`define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {`
			`entry:`
			`; CHECK-NOT: smmls`
			`%conv4 = zext i32 %a to i64`
			`%conv1 = sext i32 %b to i64`
			`%conv2 = sext i32 %c to i64`
			`%mul = mul nsw i64 %conv2, %conv1`
			`%shr5 = lshr i64 %mul, 32`
			`%sub = sub nsw i64 %conv4, %shr5`
			`%conv3 = trunc i64 %sub to i32`
			`ret i32 %conv3`
			`}`