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Remove incorrect pattern for ARM SMML instruction.
Patch by Meador Inge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156989 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3554,8 +3554,7 @@ def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
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def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
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IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
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Requires<[IsARM, HasV6]>;
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def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
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13
test/CodeGen/ARM/smml.ll
Normal file
13
test/CodeGen/ARM/smml.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
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define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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; CHECK-NOT: smmls
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%conv4 = zext i32 %a to i64
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%conv1 = sext i32 %b to i64
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%conv2 = sext i32 %c to i64
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%mul = mul nsw i64 %conv2, %conv1
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%shr5 = lshr i64 %mul, 32
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%sub = sub nsw i64 %conv4, %shr5
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%conv3 = trunc i64 %sub to i32
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ret i32 %conv3
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}
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