2012-06-04 11:27:21 +00:00
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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2011-09-08 21:05:43 +00:00
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2011-09-09 20:29:17 +00:00
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; AVX128 tests:
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_float:
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2011-09-08 21:05:43 +00:00
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;CHECK: vblendvps
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_i32:
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2011-09-08 21:05:43 +00:00
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;CHECK: vblendvps
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;CHECK: ret
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
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ret <4 x i32> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_double:
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2011-09-08 21:05:43 +00:00
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;CHECK: vblendvpd
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;CHECK: ret
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define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
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ret <2 x double> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_i64:
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2011-09-08 21:05:43 +00:00
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;CHECK: vblendvpd
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;CHECK: ret
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define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
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ret <2 x i64> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_i8:
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2011-09-08 21:05:43 +00:00
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;CHECK: vpblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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%vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
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ret <16 x i8> %vsel
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}
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2011-09-09 20:29:17 +00:00
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; AVX256 tests:
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_float8:
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2011-09-09 20:29:17 +00:00
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;CHECK: vblendvps
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;CHECK: ret
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define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
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ret <8 x float> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_i328:
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2011-09-09 20:29:17 +00:00
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;CHECK: vblendvps
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;CHECK: ret
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define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
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ret <8 x i32> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_double8:
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2011-09-09 20:29:17 +00:00
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;CHECK: vblendvpd
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;CHECK: ret
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define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
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ret <8 x double> %vsel
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}
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2013-07-18 22:47:09 +00:00
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;CHECK-LABEL: vsel_i648:
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2011-09-09 20:29:17 +00:00
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;CHECK: vblendvpd
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;CHECK: ret
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define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
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ret <8 x i64> %vsel
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}
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2011-09-12 19:30:40 +00:00
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;; TEST blend + compares
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2013-07-18 22:29:15 +00:00
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; CHECK: testa
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define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
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2011-09-12 21:24:07 +00:00
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; CHECK: vcmplepd
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2011-09-12 19:30:40 +00:00
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; CHECK: vblendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %max
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}
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2013-07-18 22:29:15 +00:00
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; CHECK: testb
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define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
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2011-09-18 00:41:38 +00:00
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; CHECK: vcmpnlepd
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2011-09-12 19:30:40 +00:00
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; CHECK: vblendvpd
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2011-09-18 00:41:38 +00:00
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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2011-09-12 19:30:40 +00:00
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}
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2011-09-09 20:29:17 +00:00
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