2010-11-12 22:42:47 +00:00
|
|
|
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
|
|
|
|
|
; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
|
|
|
|
|
; rdar://8662825
|
2007-06-21 07:40:00 +00:00
|
|
|
|
2009-03-12 05:56:37 +00:00
|
|
|
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t1:
|
2012-08-16 23:21:55 +00:00
|
|
|
; ARM: suble r1, r1, #-2147483647
|
|
|
|
|
; ARM: mov r0, r1
|
2010-11-12 22:42:47 +00:00
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t1:
|
2010-11-17 20:13:28 +00:00
|
|
|
; T2: mvn r0, #-2147483648
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: addle r1, r0
|
2012-08-16 23:21:55 +00:00
|
|
|
; T2: mov r0, r1
|
2010-11-12 22:42:47 +00:00
|
|
|
%tmp1 = icmp sgt i32 %c, 10
|
|
|
|
|
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
|
|
|
|
|
%tmp3 = add i32 %tmp2, %b
|
|
|
|
|
ret i32 %tmp3
|
2007-06-21 07:40:00 +00:00
|
|
|
}
|
|
|
|
|
|
2009-03-12 05:56:37 +00:00
|
|
|
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t2:
|
2012-08-16 23:21:55 +00:00
|
|
|
; ARM: suble r1, r1, #10
|
|
|
|
|
; ARM: mov r0, r1
|
2010-11-12 22:42:47 +00:00
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t2:
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: suble r1, #10
|
2012-08-16 23:21:55 +00:00
|
|
|
; T2: mov r0, r1
|
2010-11-12 22:42:47 +00:00
|
|
|
%tmp1 = icmp sgt i32 %c, 10
|
|
|
|
|
%tmp2 = select i1 %tmp1, i32 0, i32 10
|
|
|
|
|
%tmp3 = sub i32 %b, %tmp2
|
|
|
|
|
ret i32 %tmp3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t3:
|
Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:
(and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
(or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
(xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
The selects can then be transformed to a single predicated instruction
by peephole.
This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:16 +00:00
|
|
|
; ARM: andge r3, r3, r2
|
|
|
|
|
; ARM: mov r0, r3
|
2010-11-12 22:42:47 +00:00
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t3:
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: andge r3, r2
|
Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:
(and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
(or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
(xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
The selects can then be transformed to a single predicated instruction
by peephole.
This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:16 +00:00
|
|
|
; T2: mov r0, r3
|
2010-11-12 22:42:47 +00:00
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%z = select i1 %cond, i32 -1, i32 %x
|
|
|
|
|
%s = and i32 %z, %y
|
|
|
|
|
ret i32 %s
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t4:
|
Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:
(and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
(or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
(xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
The selects can then be transformed to a single predicated instruction
by peephole.
This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:16 +00:00
|
|
|
; ARM: orrge r3, r3, r2
|
|
|
|
|
; ARM: mov r0, r3
|
2010-11-12 22:42:47 +00:00
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t4:
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: orrge r3, r2
|
Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:
(and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
(or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
(xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
The selects can then be transformed to a single predicated instruction
by peephole.
This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:16 +00:00
|
|
|
; T2: mov r0, r3
|
2010-11-12 22:42:47 +00:00
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%z = select i1 %cond, i32 0, i32 %x
|
|
|
|
|
%s = or i32 %z, %y
|
|
|
|
|
ret i32 %s
|
2007-06-21 07:40:00 +00:00
|
|
|
}
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
|
|
|
|
|
define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
|
|
|
|
|
entry:
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t5:
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
; ARM-NOT: moveq
|
|
|
|
|
; ARM: orreq r2, r2, #1
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t5:
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
; T2-NOT: moveq
|
2012-03-20 21:49:54 +00:00
|
|
|
; T2: orreq r2, r2, #1
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
%tmp1 = icmp eq i32 %a, %b
|
|
|
|
|
%tmp2 = zext i1 %tmp1 to i32
|
|
|
|
|
%tmp3 = or i32 %tmp2, %c
|
|
|
|
|
ret i32 %tmp3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t6:
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
; ARM-NOT: movge
|
|
|
|
|
; ARM: eorlt r3, r3, r2
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t6:
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
; T2-NOT: movge
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: eorlt r3, r2
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%tmp1 = select i1 %cond, i32 %c, i32 0
|
|
|
|
|
%tmp2 = xor i32 %tmp1, %d
|
|
|
|
|
ret i32 %tmp2
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
|
|
|
|
|
entry:
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t7:
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
; ARM-NOT: lsleq
|
|
|
|
|
; ARM: andeq r2, r2, r2, lsl #1
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t7:
|
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 01:19:06 +00:00
|
|
|
; T2-NOT: lsleq.w
|
|
|
|
|
; T2: andeq.w r2, r2, r2, lsl #1
|
|
|
|
|
%tmp1 = shl i32 %c, 1
|
|
|
|
|
%cond = icmp eq i32 %a, %b
|
|
|
|
|
%tmp2 = select i1 %cond, i32 %tmp1, i32 -1
|
|
|
|
|
%tmp3 = and i32 %c, %tmp2
|
|
|
|
|
ret i32 %tmp3
|
|
|
|
|
}
|
|
|
|
|
|
2012-08-15 22:16:39 +00:00
|
|
|
; Fold ORRri into movcc.
|
|
|
|
|
define i32 @t8(i32 %a, i32 %b) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t8:
|
2012-08-15 22:16:39 +00:00
|
|
|
; ARM: cmp r0, r1
|
|
|
|
|
; ARM: orrge r0, r1, #1
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t8:
|
2012-08-15 22:16:39 +00:00
|
|
|
; T2: cmp r0, r1
|
|
|
|
|
; T2: orrge r0, r1, #1
|
|
|
|
|
%x = or i32 %b, 1
|
|
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%tmp1 = select i1 %cond, i32 %a, i32 %x
|
|
|
|
|
ret i32 %tmp1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Fold ANDrr into movcc.
|
|
|
|
|
define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t9:
|
2012-08-15 22:16:39 +00:00
|
|
|
; ARM: cmp r0, r1
|
|
|
|
|
; ARM: andge r0, r1, r2
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t9:
|
2012-08-15 22:16:39 +00:00
|
|
|
; T2: cmp r0, r1
|
|
|
|
|
; T2: andge.w r0, r1, r2
|
|
|
|
|
%x = and i32 %b, %c
|
|
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%tmp1 = select i1 %cond, i32 %a, i32 %x
|
|
|
|
|
ret i32 %tmp1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Fold EORrs into movcc.
|
|
|
|
|
define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t10:
|
2012-08-15 22:16:39 +00:00
|
|
|
; ARM: cmp r0, r1
|
|
|
|
|
; ARM: eorge r0, r1, r2, lsl #7
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t10:
|
2012-08-15 22:16:39 +00:00
|
|
|
; T2: cmp r0, r1
|
|
|
|
|
; T2: eorge.w r0, r1, r2, lsl #7
|
|
|
|
|
%s = shl i32 %c, 7
|
|
|
|
|
%x = xor i32 %b, %s
|
|
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%tmp1 = select i1 %cond, i32 %a, i32 %x
|
|
|
|
|
ret i32 %tmp1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Fold ORRri into movcc, reversing the condition.
|
|
|
|
|
define i32 @t11(i32 %a, i32 %b) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t11:
|
2012-08-15 22:16:39 +00:00
|
|
|
; ARM: cmp r0, r1
|
|
|
|
|
; ARM: orrlt r0, r1, #1
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t11:
|
2012-08-15 22:16:39 +00:00
|
|
|
; T2: cmp r0, r1
|
|
|
|
|
; T2: orrlt r0, r1, #1
|
|
|
|
|
%x = or i32 %b, 1
|
|
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%tmp1 = select i1 %cond, i32 %x, i32 %a
|
|
|
|
|
ret i32 %tmp1
|
|
|
|
|
}
|
2012-08-16 23:21:55 +00:00
|
|
|
|
|
|
|
|
; Fold ADDri12 into movcc
|
|
|
|
|
define i32 @t12(i32 %a, i32 %b) nounwind {
|
2013-07-14 06:24:09 +00:00
|
|
|
; ARM-LABEL: t12:
|
2012-08-16 23:21:55 +00:00
|
|
|
; ARM: cmp r0, r1
|
|
|
|
|
; ARM: addge r0, r1,
|
|
|
|
|
|
2013-07-14 06:24:09 +00:00
|
|
|
; T2-LABEL: t12:
|
2012-08-16 23:21:55 +00:00
|
|
|
; T2: cmp r0, r1
|
|
|
|
|
; T2: addwge r0, r1, #3000
|
|
|
|
|
%x = add i32 %b, 3000
|
|
|
|
|
%cond = icmp slt i32 %a, %b
|
|
|
|
|
%tmp1 = select i1 %cond, i32 %a, i32 %x
|
|
|
|
|
ret i32 %tmp1
|
|
|
|
|
}
|
2012-08-17 20:55:34 +00:00
|
|
|
|
|
|
|
|
; Handle frame index operands.
|
|
|
|
|
define void @pr13628() nounwind uwtable align 2 {
|
|
|
|
|
%x3 = alloca i8, i32 256, align 8
|
|
|
|
|
%x4 = load i8* undef, align 1
|
|
|
|
|
%x5 = icmp ne i8 %x4, 0
|
|
|
|
|
%x6 = select i1 %x5, i8* %x3, i8* null
|
|
|
|
|
call void @bar(i8* %x6) nounwind
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
declare void @bar(i8*)
|
Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:22 +00:00
|
|
|
|
|
|
|
|
; Fold zext i1 into predicated add
|
|
|
|
|
define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
|
|
|
|
|
entry:
|
|
|
|
|
; ARM: t13
|
|
|
|
|
; ARM: cmp r1, #10
|
|
|
|
|
; ARM: addgt r0, r0, #1
|
|
|
|
|
|
|
|
|
|
; T2: t13
|
|
|
|
|
; T2: cmp r1, #10
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: addgt r0, #1
|
Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:22 +00:00
|
|
|
%cmp = icmp sgt i32 %a, 10
|
|
|
|
|
%conv = zext i1 %cmp to i32
|
|
|
|
|
%add = add i32 %conv, %c
|
|
|
|
|
ret i32 %add
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Fold sext i1 into predicated sub
|
|
|
|
|
define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
|
|
|
|
|
entry:
|
|
|
|
|
; ARM: t14
|
|
|
|
|
; ARM: cmp r1, #10
|
|
|
|
|
; ARM: subgt r0, r0, #1
|
|
|
|
|
|
|
|
|
|
; T2: t14
|
|
|
|
|
; T2: cmp r1, #10
|
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:58:02 +00:00
|
|
|
; T2: subgt r0, #1
|
Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:22 +00:00
|
|
|
%cmp = icmp sgt i32 %a, 10
|
|
|
|
|
%conv = sext i1 %cmp to i32
|
|
|
|
|
%add = add i32 %conv, %c
|
|
|
|
|
ret i32 %add
|
|
|
|
|
}
|
