2002-01-20 22:54:45 +00:00
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/* Title: PhyRegAlloc.h -*- C++ -*-
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2001-09-08 14:22:50 +00:00
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Author: Ruchira Sasanka
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Date: Aug 20, 01
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Purpose: This is the main entry point for register allocation.
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Notes:
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2002-01-07 19:16:26 +00:00
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=====
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2001-09-08 14:22:50 +00:00
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* RegisterClasses: Each RegClass accepts a
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MachineRegClass which contains machine specific info about that register
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class. The code in the RegClass is machine independent and they use
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access functions in the MachineRegClass object passed into it to get
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machine specific info.
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* Machine dependent work: All parts of the register coloring algorithm
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except coloring of an individual node are machine independent.
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2002-01-07 19:16:26 +00:00
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Register allocation must be done as:
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2001-09-08 14:22:50 +00:00
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2002-01-07 19:16:26 +00:00
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MethodLiveVarInfo LVI(*MethodI ); // compute LV info
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LVI.analyze();
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2002-01-07 19:16:26 +00:00
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TargetMachine &target = ....
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PhyRegAlloc PRA(*MethodI, target, &LVI); // allocate regs
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PRA.allocateRegisters();
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2001-09-08 14:22:50 +00:00
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*/
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#ifndef PHY_REG_ALLOC_H
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#define PHY_REG_ALLOC_H
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#include "llvm/CodeGen/RegClass.h"
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#include "llvm/CodeGen/LiveRangeInfo.h"
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2001-10-15 16:22:44 +00:00
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#include <deque>
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class MachineCodeForMethod;
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class MachineRegInfo;
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class MethodLiveVarInfo;
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class MachineInstr;
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namespace cfg { class LoopInfo; }
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//----------------------------------------------------------------------------
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// Class AddedInstrns:
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// When register allocator inserts new instructions in to the existing
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// instruction stream, it does NOT directly modify the instruction stream.
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// Rather, it creates an object of AddedInstrns and stick it in the
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// AddedInstrMap for an existing instruction. This class contains two vectors
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// to store such instructions added before and after an existing instruction.
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//----------------------------------------------------------------------------
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2001-09-08 14:22:50 +00:00
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class AddedInstrns
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{
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public:
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std::deque<MachineInstr*> InstrnsBefore;// Added insts BEFORE an existing inst
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std::deque<MachineInstr*> InstrnsAfter; // Added insts AFTER an existing inst
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};
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typedef std::hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
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2001-10-28 18:15:12 +00:00
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//----------------------------------------------------------------------------
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// class PhyRegAlloc:
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// Main class the register allocator. Call allocateRegisters() to allocate
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// registers for a Function.
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//----------------------------------------------------------------------------
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2002-02-04 17:38:48 +00:00
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class PhyRegAlloc: public NonCopyable {
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2002-01-20 22:54:45 +00:00
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std::vector<RegClass *> RegClassList; // vector of register classes
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const TargetMachine &TM; // target machine
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const Function *Meth; // name of the function we work on
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MachineCodeForMethod &mcInfo; // descriptor for method's native code
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MethodLiveVarInfo *const LVI; // LV information for this method
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// (already computed for BBs)
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LiveRangeInfo LRI; // LR info (will be computed)
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const MachineRegInfo &MRI; // Machine Register information
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const unsigned NumOfRegClasses; // recorded here for efficiency
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2001-11-03 17:14:44 +00:00
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AddedInstrMapType AddedInstrMap; // to store instrns added in this phase
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cfg::LoopInfo *LoopDepthCalc; // to calculate loop depths
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ReservedColorListType ResColList; // A set of reserved regs if desired.
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// currently not used
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public:
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PhyRegAlloc(Function *F, const TargetMachine& TM, MethodLiveVarInfo *Lvi,
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cfg::LoopInfo *LoopDepthCalc);
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~PhyRegAlloc();
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// main method called for allocating registers
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//
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void allocateRegisters();
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2002-03-18 03:26:48 +00:00
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// access to register classes by class ID
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//
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const RegClass* getRegClassByID(unsigned int id) const {
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return RegClassList[id];
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}
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RegClass* getRegClassByID(unsigned int id) {
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return RegClassList[id]; }
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2002-02-04 17:38:48 +00:00
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private:
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2001-11-03 17:14:44 +00:00
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2002-01-07 19:16:26 +00:00
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//------- ------------------ private methods---------------------------------
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2001-09-08 14:22:50 +00:00
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2002-02-05 02:51:01 +00:00
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void addInterference(const Value *Def, const ValueSet *LVSet,
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bool isCallInst);
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2001-09-08 14:22:50 +00:00
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void addInterferencesForArgs();
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void createIGNodeListsAndIGs();
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void buildInterferenceGraphs();
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2001-10-16 01:23:19 +00:00
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2001-10-19 17:21:59 +00:00
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void setCallInterferences(const MachineInstr *MInst,
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const ValueSet *LVSetAft );
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2001-10-23 21:38:42 +00:00
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void move2DelayedInstr(const MachineInstr *OrigMI,
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const MachineInstr *DelayedMI );
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2001-10-19 21:42:06 +00:00
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void markUnusableSugColors();
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2001-10-28 18:15:12 +00:00
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void allocateStackSpace4SpilledLRs();
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2001-11-08 20:55:05 +00:00
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void insertCode4SpilledLR (const LiveRange *LR,
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MachineInstr *MInst,
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const BasicBlock *BB,
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const unsigned OpNum);
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2001-10-19 21:42:06 +00:00
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2002-01-20 22:54:45 +00:00
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inline void constructLiveRanges() { LRI.constructLiveRanges(); }
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void colorIncomingArgs();
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2001-09-30 23:19:57 +00:00
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void colorCallRetArgs();
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2001-09-08 14:22:50 +00:00
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void updateMachineCode();
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2001-09-30 23:19:57 +00:00
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2001-09-15 19:08:41 +00:00
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void printLabel(const Value *const Val);
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void printMachineCode();
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2001-10-28 18:15:12 +00:00
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friend class UltraSparcRegInfo;
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2001-11-03 20:41:22 +00:00
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2002-02-05 02:51:01 +00:00
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int getUsableUniRegAtMI(RegClass *RC, int RegType,
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const MachineInstr *MInst,
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const ValueSet *LVSetBef, MachineInstr *&MIBef,
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MachineInstr *&MIAft );
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2001-11-03 20:41:22 +00:00
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2001-11-15 20:22:37 +00:00
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int getUnusedUniRegAtMI(RegClass *RC, const MachineInstr *MInst,
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const ValueSet *LVSetBef);
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2001-11-03 20:41:22 +00:00
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2001-11-15 20:22:37 +00:00
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void setRelRegsUsedByThisInst(RegClass *RC, const MachineInstr *MInst );
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int getUniRegNotUsedByThisInst(RegClass *RC, const MachineInstr *MInst);
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2001-10-28 18:15:12 +00:00
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2001-11-14 15:37:13 +00:00
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void addInterf4PseudoInstr(const MachineInstr *MInst);
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};
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#endif
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