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Fix a ValueTracking rule: RHS means operand 1, not 0. Add a simple
ashr instcombine to help expose this code. And apply the fix to SelectionDAG's copy of this code too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65364 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -625,7 +625,7 @@ unsigned llvm::ComputeNumSignBits(Value *V, TargetData *TD, unsigned Depth) {
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if (Tmp == 1) return 1; // Early out.
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// Special case decrementing a value (ADD X, -1):
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if (ConstantInt *CRHS = dyn_cast<ConstantInt>(U->getOperand(0)))
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if (ConstantInt *CRHS = dyn_cast<ConstantInt>(U->getOperand(1)))
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if (CRHS->isAllOnesValue()) {
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APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0);
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APInt Mask = APInt::getAllOnesValue(TyBits);
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@ -2008,7 +2008,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
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if (Tmp == 1) return 1; // Early out.
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// Special case decrementing a value (ADD X, -1):
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if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
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if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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if (CRHS->isAllOnesValue()) {
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APInt KnownZero, KnownOne;
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APInt Mask = APInt::getAllOnesValue(VTBits);
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@ -7031,7 +7031,12 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) {
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MaskedValueIsZero(Op0,
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APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())))
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return BinaryOperator::CreateLShr(Op0, I.getOperand(1));
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// Arithmetic shifting an all-sign-bit value is a no-op.
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unsigned NumSignBits = ComputeNumSignBits(Op0);
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if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits())
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return ReplaceInstUsesWith(I, Op0);
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return 0;
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}
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8
test/Transforms/InstCombine/ashr-nop.ll
Normal file
8
test/Transforms/InstCombine/ashr-nop.ll
Normal file
@ -0,0 +1,8 @@
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; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep ashr
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define i32 @foo(i32 %x) {
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%o = and i32 %x, 1
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%n = add i32 %o, -1
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%t = ashr i32 %n, 17
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ret i32 %t
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}
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