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AVX-512: fixed a bug in arithmetic operations lowering for i1 type

Browse Source 
https://llvm.org/bugs/show_bug.cgi?id=23630



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2015-05-26 12:37:17 +00:00
parent 9ed9b04cea
commit 001a2ba63f
1 changed files with 12 additions and 0 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -1266,6 +1266,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::XOR, MVT::i1, Legal);
setOperationAction(ISD::OR, MVT::i1, Legal);
setOperationAction(ISD::AND, MVT::i1, Legal);
setOperationAction(ISD::SUB, MVT::i1, Custom);
setOperationAction(ISD::ADD, MVT::i1, Custom);
setOperationAction(ISD::MUL, MVT::i1, Custom);
setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
@ -16180,6 +16183,9 @@ static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
}
static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::i1)
return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
Op.getOperand(0), Op.getOperand(1));
assert(Op.getSimpleValueType().is256BitVector() &&
Op.getSimpleValueType().isInteger() &&
"Only handle AVX 256-bit vector integer operation");
@ -16187,6 +16193,9 @@ static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
}
static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType() == MVT::i1)
return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
Op.getOperand(0), Op.getOperand(1));
assert(Op.getSimpleValueType().is256BitVector() &&
Op.getSimpleValueType().isInteger() &&
"Only handle AVX 256-bit vector integer operation");
@ -16198,6 +16207,9 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
SDLoc dl(Op);
MVT VT = Op.getSimpleValueType();
if (VT == MVT::i1)
return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
// Decompose 256-bit ops into smaller 128-bit ops.
if (VT.is256BitVector() && !Subtarget->hasInt256())
return Lower256IntArith(Op, DAG);