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Thumb assembly parsing and encoding for ASR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2693,7 +2693,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
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// Next, determine if we have a carry setting bit. We explicitly ignore all
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// the instructions we know end in 's'.
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if (Mnemonic.endswith("s") &&
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!(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
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!(Mnemonic == "cps" || Mnemonic == "mls" ||
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Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
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Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
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Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
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@ -56,3 +56,23 @@ _func:
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@ CHECK: adr r2, _baz @ encoding: [A,0xa2]
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@ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
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@------------------------------------------------------------------------------
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@ ASR (immediate)
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@------------------------------------------------------------------------------
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asrs r2, r3, #32
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asrs r2, r3, #5
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asrs r2, r3, #1
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@ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
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@ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
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@ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
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@------------------------------------------------------------------------------
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@ ASR (register)
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@------------------------------------------------------------------------------
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asrs r5, r2
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@ CHECK: asrs r5, r2 @ encoding: [0x15,0x41]
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@ -18,3 +18,14 @@
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@ CHECK-ERRORS: error: instruction variant requires ARMv6 or later
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@ CHECK-ERRORS: mov r2, r3
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@ CHECK-ERRORS: ^
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@ Out of range immediates for ASR instruction.
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asrs r2, r3, #33
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asrs r2, r3, #0
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #0
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@ CHECK-ERRORS: ^
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