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[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -256,6 +256,12 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
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case Mips::JALR64:
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// jalr $ra, $r1 => jalr $r1
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return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
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case Mips::NOR:
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// nor $r0, $r1, $zero => not $r0, $r1
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return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
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case Mips::NOR64:
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// nor $r0, $r1, $zero => not $r0, $r1
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return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
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case Mips::OR:
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// or $r0, $r1, $zero => move $r0, $r1
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return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
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@ -96,12 +96,15 @@ def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
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ADD_FM<0, 0x2d>;
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def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
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ADD_FM<0, 0x2f>;
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let isCodeGenOnly = 1 in {
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def SLT64 : SetCC_R<"slt", setlt, CPU64RegsOpnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, CPU64RegsOpnd>, ADD_FM<0, 0x2b>;
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def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
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def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
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}
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/// Shift Instructions
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def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
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@ -334,36 +337,12 @@ def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
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def : InstAlias<"move $dst, $src",
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(DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"and $rs, $rt, $imm",
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(ANDi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
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1>,
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Requires<[HasMips64]>;
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def : InstAlias<"slt $rs, $rt, $imm",
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(SLTi64 CPURegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
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1>,
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Requires<[HasMips64]>;
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def : InstAlias<"not $rt, $rs",
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(NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"j $rs", (JR64 CPU64RegsOpnd:$rs), 0>, Requires<[HasMips64]>;
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def : InstAlias<"daddu $rs, $rt, $imm",
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(DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
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1>;
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0>;
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def : InstAlias<"dadd $rs, $rt, $imm",
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(DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
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1>;
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def : InstAlias<"or $rs, $rt, $imm",
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(ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
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1>, Requires<[HasMips64]>;
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def : InstAlias<"bnez $rs,$offset",
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(BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"beqz $rs,$offset",
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(BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
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Requires<[HasMips64]>;
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0>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64" in {
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@ -1105,20 +1105,19 @@ def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
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def : InstAlias<"move $dst, $src",
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(ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
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Requires<[NotMips64]>;
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def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>;
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def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
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def : InstAlias<"addu $rs, $rt, $imm",
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(ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"add $rs, $rt, $imm",
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(ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"and $rs, $rt, $imm",
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(ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"j $rs", (JR CPURegsOpnd:$rs), 0>,
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Requires<[NotMips64]>;
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def : InstAlias<"j $rs", (JR CPURegsOpnd:$rs), 0>;
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def : InstAlias<"jalr $rs", (JALR RA, CPURegsOpnd:$rs), 0>;
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def : InstAlias<"jal $rs", (JALR RA, CPURegsOpnd:$rs), 0>;
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def : InstAlias<"jal $rd,$rs", (JALR CPURegsOpnd:$rd, CPURegsOpnd:$rs), 0>;
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def : InstAlias<"not $rt, $rs",
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(NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
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(NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 0>;
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def : InstAlias<"neg $rt, $rs",
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(SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
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def : InstAlias<"negu $rt, $rs",
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@ -1126,11 +1125,9 @@ def : InstAlias<"negu $rt, $rs",
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def : InstAlias<"slt $rs, $rt, $imm",
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(SLTi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
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Requires<[NotMips64]>;
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(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 0>;
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def : InstAlias<"or $rs, $rt, $imm",
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(ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
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Requires<[NotMips64]>;
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(ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 0>;
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def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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def : InstAlias<"mfc0 $rt, $rd",
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(MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
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@ -1141,11 +1138,9 @@ def : InstAlias<"mfc2 $rt, $rd",
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def : InstAlias<"mtc2 $rt, $rd",
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(MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
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def : InstAlias<"bnez $rs,$offset",
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(BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
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Requires<[NotMips64]>;
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(BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 0>;
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def : InstAlias<"beqz $rs,$offset",
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(BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
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Requires<[NotMips64]>;
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(BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 0>;
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def : InstAlias<"syscall", (SYSCALL 0), 1>;
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def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
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