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Before implementing copyfromreg, we'll implement copytoreg correctly.

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This gets us this for the previous testcase:

_test:
        lis r2, 0
        ori r3, r2, 65535
        blr

Note that we actually write to r3 (the return reg) correctly now :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22933 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-08-19 20:50:53 +00:00
parent 4ccd406317
commit 0189197608
1 changed files with 6 additions and 2 deletions
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8
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@@ -36,14 +36,16 @@ namespace {
MachineBasicBlock *BB; MachineBasicBlock *BB;
const TargetMachine &TM; const TargetMachine &TM;
const TargetInstrInfo &TII; const TargetInstrInfo &TII;
const MRegisterInfo &MRI;
SSARegMap *RegMap; SSARegMap *RegMap;
std::map<SDNode *, unsigned> EmittedOps; std::map<SDNode *, unsigned> EmittedOps;
public: public:
SimpleSched(SelectionDAG &D, MachineBasicBlock *bb) SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()), : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
RegMap(BB->getParent()->getSSARegMap()) { MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
assert(&TII && "Target doesn't provide instr info?"); assert(&TII && "Target doesn't provide instr info?");
assert(&MRI && "Target doesn't provide register info?");
} }
void Run() { void Run() {
@@ -131,7 +133,9 @@ unsigned SimpleSched::Emit(SDOperand Op) {
case ISD::EntryToken: break; case ISD::EntryToken: break;
case ISD::CopyToReg: { case ISD::CopyToReg: {
unsigned Val = Emit(Op.getOperand(2)); unsigned Val = Emit(Op.getOperand(2));
// FIXME: DO THE COPY NOW. MRI.copyRegToReg(*BB, BB->end(),
cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
RegMap->getRegClass(Val));
break; break;
} }
} }