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Use multiple virtual registers in PPC CR spilling
Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1094,6 +1094,13 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
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RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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RC->getAlignment(),
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false));
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false));
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// These kinds of spills might need two registers.
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if (spillsCR(MF) || spillsVRSAVE(MF))
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RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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false));
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}
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}
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}
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}
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@ -304,14 +304,14 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
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MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
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MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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bool LP64 = Subtarget.isPPC64();
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bool LP64 = Subtarget.isPPC64();
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unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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unsigned SrcReg = MI.getOperand(0).getReg();
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unsigned SrcReg = MI.getOperand(0).getReg();
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// We need to store the CR in the low 4-bits of the saved value. First, issue
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// We need to store the CR in the low 4-bits of the saved value. First, issue
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@ -321,13 +321,17 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
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// If the saved register wasn't CR0, shift the bits left so that they are in
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// If the saved register wasn't CR0, shift the bits left so that they are in
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// CR0's slot.
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// CR0's slot.
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if (SrcReg != PPC::CR0)
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if (SrcReg != PPC::CR0) {
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unsigned Reg1 = Reg;
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Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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// rlwinm rA, rA, ShiftBits, 0, 31.
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// rlwinm rA, rA, ShiftBits, 0, 31.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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.addReg(Reg, RegState::Kill)
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.addReg(Reg1, RegState::Kill)
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.addImm(getPPCRegisterNumbering(SrcReg) * 4)
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.addImm(getPPCRegisterNumbering(SrcReg) * 4)
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.addImm(0)
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.addImm(0)
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.addImm(31);
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.addImm(31);
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}
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addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
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addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
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.addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
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.addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
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@ -343,14 +347,14 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
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MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
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MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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bool LP64 = Subtarget.isPPC64();
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bool LP64 = Subtarget.isPPC64();
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unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned DestReg = MI.getOperand(0).getReg();
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assert(MI.definesRegister(DestReg) &&
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assert(MI.definesRegister(DestReg) &&
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"RESTORE_CR does not define its destination");
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"RESTORE_CR does not define its destination");
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@ -361,15 +365,18 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
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// If the reloaded register isn't CR0, shift the bits right so that they are
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// If the reloaded register isn't CR0, shift the bits right so that they are
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// in the right CR's slot.
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// in the right CR's slot.
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if (DestReg != PPC::CR0) {
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if (DestReg != PPC::CR0) {
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unsigned Reg1 = Reg;
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Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
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unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
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// rlwinm r11, r11, 32-ShiftBits, 0, 31.
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// rlwinm r11, r11, 32-ShiftBits, 0, 31.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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.addReg(Reg).addImm(32-ShiftBits).addImm(0)
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.addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
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.addImm(31);
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.addImm(31);
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}
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}
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
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.addReg(Reg);
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.addReg(Reg, RegState::Kill);
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// Discard the pseudo instruction.
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// Discard the pseudo instruction.
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MBB.erase(II);
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MBB.erase(II);
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@ -381,13 +388,11 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
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MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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// scavenger can return multiple registers, stop using reserved registers
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unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
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// here.
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unsigned Reg = PPC::R0;
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unsigned SrcReg = MI.getOperand(0).getReg();
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unsigned SrcReg = MI.getOperand(0).getReg();
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BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
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BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
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@ -407,13 +412,11 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
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MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
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MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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// scavenger can return multiple registers, stop using reserved registers
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unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
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// here.
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unsigned Reg = PPC::R0;
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned DestReg = MI.getOperand(0).getReg();
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assert(MI.definesRegister(DestReg) &&
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assert(MI.definesRegister(DestReg) &&
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"RESTORE_VRSAVE does not define its destination");
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"RESTORE_VRSAVE does not define its destination");
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@ -422,7 +425,7 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
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Reg), FrameIndex);
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Reg), FrameIndex);
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BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
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BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
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.addReg(Reg);
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.addReg(Reg, RegState::Kill);
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// Discard the pseudo instruction.
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// Discard the pseudo instruction.
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MBB.erase(II);
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MBB.erase(II);
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@ -2,21 +2,22 @@
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; ModuleID = 'hh.c'
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; ModuleID = 'hh.c'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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target triple = "powerpc-apple-darwin9.6"
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target triple = "powerpc-apple-darwin9.6"
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; This formerly used R0 for both the stack address and CR.
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define void @foo() nounwind {
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define void @foo() nounwind {
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entry:
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entry:
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;CHECK: mfcr r0
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; Note that part of what is being checked here is proper register reuse.
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;CHECK: lis r2, 1
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; CHECK: mfcr [[T1:r[0-9]+]] ; cr2
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;CHECK: rlwinm r0, r0, 8, 0, 31
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; CHECK: lis [[T2:r[0-9]+]], 1
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;CHECK: ori r2, r2, 34540
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; FIXME: There should only be one lis needed here!
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;CHECK: stwx r0, r1, r2
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; CHECK: lis [[T3:r[0-9]+]], 1
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; Make sure that the register scavenger returns the same temporary register.
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; CHECK: addi r3, r1, 72
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;CHECK: lis r2, 1
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; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31
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;CHECK: mfcr r0
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; CHECK: ori [[T2]], [[T2]], 34540
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;CHECK: ori r2, r2, 34536
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; CHECK: ori [[T3]], [[T3]], 34536
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;CHECK: rlwinm r0, r0, 12, 0, 31
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; CHECK: stwx [[T1]], r1, [[T2]]
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;CHECK: stwx r0, r1, r2
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; CHECK: mfcr [[T4:r[0-9]+]] ; cr3
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; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31
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; CHECK: stwx r4, r1, [[T3]]
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%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
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%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
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%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
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@ -25,11 +26,16 @@ entry:
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br label %return
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br label %return
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return: ; preds = %entry
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return: ; preds = %entry
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;CHECK: lis r2, 1
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; CHECK: lis [[T1:r[0-9]+]], 1
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;CHECK: ori r2, r2, 34540
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; CHECK: ori [[T1]], [[T1]], 34536
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;CHECK: lwzx r0, r1, r2
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; CHECK: lwzx [[T1]], r1, [[T1]]
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;CHECK: rlwinm r0, r0, 24, 0, 31
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; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31
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;CHECK: mtcrf 32, r0
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; CHECK: mtcrf 16, [[T1]]
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; CHECK: lis [[T1]], 1
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; CHECK: ori [[T1]], [[T1]], 34540
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; CHECK: lwzx [[T1]], r1, [[T1]]
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; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31
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; CHECK: mtcrf 32, [[T1]]
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ret void
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ret void
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}
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}
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